Hybrid Silicon Lasers
G¨unther Roelkens
1
, Yannick De Koninck
1
, Shahram Keyvaninia
1
, Stevan Stankovic
1
, Martijn
Tassaert
1
, Marco Lamponi
2
, Guanghua Duan
2
, Dries Van Thourhout
1
and Roel Baets
1
1
Department of Information Technology, Photonics Research Group, Ghent University - IMEC
Sint-Pietersnieuwstraat 41 B-9000 Ghent, Belgium
2
Alcatel-Thales III-V labs, Campus Polytechnique, 1, Avenue A. Fresnel, 91767 Palaiseau
cedex, France
ABSTRACT
Hybrid silicon lasers based on bonded III-V layers on silicon are discussed with respect to the challenges and
trade-offs in their design and fabrication. Focus is on specific designs that combine good light confinement in
the gain layer with good spectral control provided by grating structures patterned in silicon.
1. INTRODUCTION
Silicon-based photonic integrated circuits are gaining considerable importance for a variety of applications, from
telecommunications to sensors. The interest in this technology stems mostly from the expectation that the ma-
turity and low cost of CMOS-technology can be applied for advanced photonics products. Other driving forces
for silicon photonics include the design richness associated with high refractive index contrast as well as the
potential for integration of photonics with electronics.
Building light sources, and in particular laser sources, on integrated silicon circuits is a long sought goal,
on one hand in order to complete the functionality of the integrated circuit with one or several light sources
but on the other hand also as a manufacturing approach for lasers on large wafers in CMOS-fabs. In terms
of device performance the most successful approach to date is definitely the hybrid (also called heterogeneous)
III-V on silicon laser. In this device thin layers of III-V semiconductors are bonded to silicon. The laser cavity
gets its gain from the III-V layers but couples its output light into a silicon waveguide. Often part of the cavity
structure is implemented by means of patterning in silicon, thereby taking advantage of the resolution and accu-
racy of lithography tools in CMOS fabs. In that sense these hybrid III-V/silicon lasers take the best of two worlds.
In spite of rapid progress in this field since about 2006 the design and fabrication of hybrid silicon lasers
present specific challenges and trade-offs. There are many choices to be made, both in terms of the cavity struc-
ture, the optical coupling between the silicon waveguide and the III-V waveguide and the technological approach.
A relatively large variety of approaches have been reported in the past years.
In this paper we will first review the options in the design of hybrid laser cavities, with emphasis on the
light distribution in and the light exchange between the silicon and III-V layer. This will be followed by a
section on the technological challenges presented by the bonding process. We will then focus on specific designs
that combine good light confinement in the gain layer with good spectral control provided by grating structures
patterned in silicon.
2. HYBRID LASER CAVITY DESIGN
Although the basic device cross-section, a III-V epitaxial layer transferred to a silicon-on-insulator waveguide
wafer, is very simple, there is a large degree of freedom in the design of the laser cavity. Particularly, in the
design a choice needs to be made whether the optical mode is predominantly confined in the silicon waveguide
or in the III-V overlay. Both options have their advantages and disadvantages and they are not even mutually
exclusive, given the fact that e.g. adiabatic tapers inside the laser cavity can be used to change the optical
confinement in the respective layers. Confining the optical mode predominantly in the silicon waveguide layer
has the advantage of making the coupling to a passive silicon waveguide straightforward. Moreover, wavelength
selective features can easily be defined in the silicon waveguide layer using CMOS fabrication techniques, which
provides an accurate mechanism to control the emission wavelength of the laser. A drawback of this silicon-
confined approach however is that only a small fraction of the optical mode interacts with the gain material,
resulting in longer laser cavities and higher power consumption devices. This type of laser cavity is illustrated
in figure 1(a).
1
On the other side of the design space, one can find III-V on silicon laser geometries, where
the optical mode is completely confined in the III-V waveguide layer and where the optical cavity is defined
in the III-V semiconductor. A representative example of such a laser geometry is the III-V microdisk laser
heterogeneously integrated on a silicon waveguide layer, shown in figure 1(b).
2
This laser geometry allows
making ultra-compact light sources, given the high confinement of the optical mode in the gain material, while
the coupling to the silicon waveguide layer is achieved through an intra-cavity evanescent coupling scheme. The
wavelength of emission is determined by the diameter of the III-V microdisk, which makes it less straightforward
to effectively control this emission wavelength. Given these two extreme cases in the design space and their
respective advantages and disadvantages, in the remainder of this paper we will present laser geometries that
combine the best of both worlds, i.e. high optical confinement in the gain material, combined with a wavelength
selective feedback mechanism defined in the silicon waveguide layer. But before that, we will elaborate on the
technological challenges to integrate the III-V epitaxial layer structure on top of the silicon waveguide layer.
Figure 1. Two examples of choices made inside the laser design space: a silicon-confined III-V/silicon laser (a) and a III-V
confined III-V/silicon laser geometry (b)
3. HYBRID LASERS INTEGRATION TECHNIQUES
The integration of III-V material on the SOI platform is a prerequisite for the fabrication of hybrid lasers, but it
also presents a technological challenge. In general, the three main approaches for solving this problem are flip-
chip integration, hetero-epitaxial growth and bonding of III-V material on a SOI wafer. In the case of flip-chip
integration, a pre-fabricated photonic component is flipped over and bonded to SOI using solder bumps. This
approach has been suggested for the integration of III-V lasers on SOI,
3
but such integration technique requires
precise alignment and sequential attachment of individual devices. It is therefore time-consuming and costly
for large scale integration of photonic devices on a single SOI wafer. On the other hand, the hetero-epitaxial
growth of III-V on the SOI platform offers a possibility for large scale, high density integration and wafer-scale
processing of photonic devices, after the functional III-V layers are grown. This eliminates the need for the
precise alignment and allows simultaneous device processing and high-throughput fabrication. However, the lat-
tice mismatch between III-V materials and silicon makes this approach not straightforward, given the formation
of defects in the grown epitaxial layers.
4
Continuous improvements are being made however to mitigate the
issues associated with the lattice mismatch,
5
and it remains to be seen whether this approach is viable in an
industrial-scale fabrication process.
Considering the drawbacks and limitations of flip-chip and hetero-epitaxial growth today, the bonding of III-
V material on a SOI wafer remains the most promising and the most commonly used method for the fabrication
of hybrid III-V/Si lasers. In this approach, two different integration strategies can be followed. In the first one,
a pre-processed, or partially processed photonic component can be bonded on the SOI waveguide platform. Like
the flip-chip integration, this approach imposes very stringent alignment requirements. Hybrid lasers based on
metallic bonding of pre-fabricated III-V DFB lasers on SOI waveguides were recently demonstrated,
6
but their
fabrication requires a sub-micron precision bonding procedure. Therefore, the preferred strategy is to first bond
unprocessed layers of III-V material on the SOI and then perform wafer-scale processing of the devices, by means
of standard lithographic procedures. In this way, no precise bonding alignment is required and the simultaneous
processing of a multitude of devices on a single SOI wafer is feasible, with a high yield and high integration density.
Figure 2. Process flow of the device fabrication with the III-V/SOI die-to-wafer bonding technology (a) and process flow
of a die-to-die BCB bonding process (b)
Traditionally, bonding techniques were developed for wafer-to-wafer bonding. However, due to the wafer
size mismatch and the fact that most of III-V material is lost in the subsequent processing, this approach is
not very cost-effective, unless the largest fraction of the SOI waveguide circuit requires the presence of III-V
semiconductor. Alternatively, multiple die-to-wafer bonding gives an opportunity to bond individual III-V dies
on specific locations on a SOI wafer where they are actually needed. In this way, III-V material is used in a much
more efficient manner. Schematically, this method is illustrated in figure 2(a). Following the surface preparation,
individual III-V dies are bonded on a processed SOI wafer with the passive photonic components. After the
bonding, the InP substrate is removed by combination of mechanical grinding and chemical wet-etching. An
etch stop layer is used to separate the substrate from the functional layers. Subsequently, III-V processing of
the opto-electronic components can be done on a wafer-scale.
The two most commonly used bonding techniques are direct (or molecular) bonding and adhesive bonding.
Direct bonding is based on intermolecular van der Waals forces that tend to keep molecules together, when
they are sufficiently close to each other, usually below 0.5 nm. Therefore, an effective direct bonding between a
III-V and SOI wafers requires very flat, ultimately clean surfaces in order to get the different wafers into such
an intimate contact. This is a well-known technique, successfully used for fabrication of SOI wafers for almost
a decade, with a high yield. The bonding of III-V semiconductors onto processed SOI waveguide wafers can
however pose additional problems in terms of yield, given the lower-quality surfaces. Therefore, our research
effort focuses on the use of adhesive wafer bonding. Compared to the direct bonding, the use of an adhesive
bonding agent generally gives much more relaxed requirements for the bonding surface roughness, topography
and particle contamination. Various adhesives can be used for the wafer bonding,
7
but since it is preferred to
have post-bonding processing of III-V material on top of SOI, adhesives that provide sufficiently high thermal
budget (up to 400
◦
C) should be used. Therefore, we focus on the use of BCB, given its superior characteristics.
8
BCB is well-known in electronics industry and provides sufficient thermal budget, low optical loss at telecom-
munication wavelengths and low shrinkage upon curing. Several device demonstrations have been made based
on this adhesive bonding approach, including photodetectors
9, 10
and lasers.
11, 12
As a general illustration of a BCB bonding process, a die-to-die bonding procedure is presented in Figure
2(b). After cleaning the SOI surface (using SC-1 solution), a BCB solution (in mesitylene) is spin-coated on the
SOI wafer (or a die). The liquid BCB solution can planarize the SOI wafer topography and sufficiently small
particles can be incorporated in the adhesive film, not compromising the bonding quality. After spin-coating,
the BCB is baked at 150
◦
C to evaporate the solvent and settle the applied film. After this, a sacrificial layer on
top of the III-V die (or wafer) is removed by wet etching and the III-V die is attached on the SOI after which
the whole stack is placed in an oven where the BCB is cured in a nitrogen atmosphere at 250
◦
C for 1 hour.
Usually, a pressure of 200-300 kPa is applied during the curing.
Figure 3. Bonding results in the case of very thin BCB layers: (a) III-V thin film bonded on a patterned SOI die with a
very high yield; (b) SEM image of the III-V film on top of the SOI waveguide, with a 45nm-thick BCB bonding layer.
The relaxed wafer quality requirements in the adhesive wafer bonding process are especially valid in the case
where the BCB bonding layers are several hundred nanometers thick. However, as the bonding layers become
thinner, the requirements become more stringent, as larger particles cannot be tolerated and the SOI wafer
topography starts to play a more significant role. Specifically the realization of evanescently-coupled photonic
devices requires very thin bonding layers (< 100 nm) with high uniformity. Recently, very thin BCB bonding
layers, suitable for the fabrication of evanescently-coupled hybrid III-V/Si lasers have been demonstrated, both
in the case of bonding a III-V wafer
13
and a III-V die
14
on SOI waveguide circuits.
The uniformity of the bonding layer is of paramount importance. The latest results demonstrate that even
in the case of bonding a relatively large III-V die (8mm x 7 mm) on top of the SOI waveguides, good BCB layer
uniformity can be achieved, retaining high bonding yield and very thin BCB layers (see Figure 3).
14
Variations in
the BCB bonding layer thickness are usually within several nanometers and well within the range that is required
for evanescently-coupled photonics devices. This shows that the BCB bonding technique is able to match direct
bonding when ultra-thin bonding layers are required for evanescently-coupled devices, while also being able to
achieve thicker bonding layers for other opto-electronic devices.
4. COUPLING MECHANISMS
As mentioned before, an optimal laser cavity design should consist of a section where the optical mode is
completely confined to the III-V waveguide layer, while the wavelength selective feedback is provided by structures
defined in the silicon. Of course, the laser emission should also be coupled efficiently into the silicon waveguide
layer. In this section we will present a few laser cavity designs that fulfill these requirements. This includes an
adiabatic tapered coupling to transform the optical mode from a III-V confined optical mode to a silicon confined
optical mode, a broadband grating based reflector for the realization of a hybrid silicon modelocked laser and
the use of resonant grating reflectors for the wavelength selective feedback and outcoupling.
4.1 Adiabatically tapered coupling
A relatively straightforward method to achieve a high performance laser cavity is to use an intra-cavity double
taper structure, using taper-based mode transformers in both the III-V and silicon waveguides.
15
Mode coupling
occurs in the tapered region, while light generation and amplification take place in the III-V waveguide. This
approach allows for the incorporation of wavelength selective feedback structures in the silicon waveguide layer,
such as gratings and ring resonators, while it provides at the same time also an efficient way of coupling to a
passive silicon waveguide circuit outside the laser cavity. If we consider half of the device structure (figure 4(a)),
the structure can be divided into three parts. In the section (1), there is a III-V waveguide that provides optical
gain. At right side of it, there is a coupling region that couples light from one waveguide to the other. Section
(3) is a silicon waveguide without III-V on top.
Figure 4. The schematic of an adiabatically tapered III-V/silicon laser (a) and the evolution of the optical mode profile
throughout the taper structure (b)
The III-V region consists of a standard multiple quantum well (QW) double heterostructure, which consists
of a p-InGaAs contact layer, a p-InP clad (1.5µm), 6 InGaAsP QW surrounded by two InGaAsP separate
confinement heterostructure (SCH) layers (with a total thickness of 320nm), and an n-InP layer (200nm). The
SOI substrate consists of a 400nm thick silicon waveguide layer on top of a 2µm thick buried oxide layer. The
silicon rib waveguides have an etch depth of 180nm and a width of 1µm. In our design, the underlying silicon rib
waveguide (length L = 150 µm) is tapering from 1 µm width to 400nm. The III-V adiabatic taper is a piecewise
linear taper tapering from 2µm width downto 900nm width (length L
tap
=20 µm) and from 900nm width to
500nm width again with length L. This 500nm wide taper tip, combined with the deep etching, makes the
fabrication of such a device not straightforward. The required length of the taper depends on the BCB bonding
layer thickness. Full vectorial calculations show that, assuming a bonding layer thickness below 100nm and
perfect alignment between the silicon waveguide and the III-V waveguide, a taper length L of 150µm should be
sufficient for adiabatic mode conversion. A first prototype of such a device, not yet incorporating the wavelength
selective feedback structure, was recently demonstrated.
15
A Fabry-Perot hybrid III-V/silicon laser was realized
by defining the mirrors on the passive SOI waveguides by cleaving the SOI wafer. The device was mounted on
a temperature controlled stage set to 290K. The output laser beam is collected by a lens fiber coupled to the
silicon waveguide cleaved facet. The coupling losses are estimated to be higher than 5dB. The L-I curve is shown
