Patent
Independently controlled, double gate nanowire memory cell with self-aligned contacts
Ibrahim Ban,Peter L. D. Chang +1 more
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TLDR
In this article, a doubled gate, dynamic storage device and method of fabrication are described, where a back bias gate surrounded three sides of a semiconductor body with a front gate disposed on the remaining surface.Abstract:
A doubled gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.read more
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Nanowire field-effect transistors
TL;DR: In this article, a method for forming a nanowire field effect transistor (FET) device was proposed, which includes forming a first silicon on insulator (SOI) pad region, a second SOI portion connecting the first SOI pad region to the second SoI portion on a substrate, patterning a first hardmask layer over the secondSOI portion, forming a suspended nanowires over the semiconductor substrate, and a second gate structure around a portion of the first suspended nano-connector.
Patent
Floating body memory cell having gates favoring different conductivity type regions
TL;DR: In this article, a method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used, is described.
Patent
Gate-All-Around Nanowire Tunnel Field Effect Transistors
TL;DR: In this paper, a method for forming a nanowire tunnel field effect transistor (FET) device is described, where the nanowires are suspended by first and second pad regions over a semiconductor substrate.
Patent
Gate-All-Around Nanowire Field Effect Transistors
TL;DR: In this article, a method for forming a nanowire field effect transistor (FET) device is described, which includes forming a suspended nanowires over a semiconductor substrate, forming a gate structure around a portion of the nanowired, forming an additional spacer adjacent to the sidewalls of the gate and around portions of the wires extending from the gate, and epitaxially growing a doped semiconductor material on exposed cross sections of the wire.
Patent
Semiconductor device with isolated body portion
Annalisa Cappellani,Stephen M. Cea,Tahir Ghani,Harry Gomez,Jack T. Kavalieros,Patrick H. Keys,Seyiyon Kim,Kelin J. Kuhn,Lilak Aaron D,Rafael Rios,Mayank Sahni +10 more
TL;DR: In this article, isolated body portions of semiconductor devices with isolated body regions are described, where the semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region.
References
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Semiconductor memory device
TL;DR: In this article, the authors proposed a semiconductor memory device which can be operated with low power source voltage such that write-in speed is not reduced and of which power consumption is low.
Patent
Semiconductor device having high drive current and method of manufacture therefor
TL;DR: In this article, the authors proposed a method for forming a first semiconductor device in a substrate, where a gate structure, a spacer disposed on the sidewalls of the gate structure and recessed source and drain regions disposed on either side of the gated gate structure are formed.
Patent
Semiconductor integrated circuit device
TL;DR: In this paper, the authors proposed a bus switch that can reduce the influence exerted by reflected wave by optimizing the continuity resistances of transistors constituting a bus switching switch in a semiconductor integrated circuit device.
Patent
Field effect transistors having multiple stacked channels
TL;DR: In this article, a pre-active pattern is constructed on a surface of a substrate and an active channel pattern is used to define at least one tunnel between adjacent channels, and a gate electrode is formed in the tunnels and surrounding the channels.
Patent
Method of forming semiconductor device having a GAA type transistor
TL;DR: In this paper, the etch stopping layer pattern is removed at the gate region crossing the active layer pattern at the channel region, to expose the buried oxide layer and a conductive material fills the cavity.