Journal ArticleDOI
Low-Power and Area-Efficient Shift Register Using Pulsed Latches
TLDR
The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops and uses a small number of the pulsed clock signals instead of the conventional single pulsing clock signal.Abstract:
This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 $\mu{\rm m}$ CMOS process with ${\rm V}_{\rm DD}=1.8{\rm V}$ . The core area is $6600\ \mu{\rm m}^{2}$ . The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops.read more
Citations
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Journal ArticleDOI
Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design Techniques
TL;DR: A semi-automatic short path padding flow is built around this idea, and used to design: 1) ISCAS benchmark circuits and 2) an 8-bit 8-tap finite impulse response (FIR) core, the latter fabricated in a 65-nm CMOS technology.
Journal ArticleDOI
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches
TL;DR: The proposed biddirectional shift-register reduces the area and power consumption by replacing master–slave flip-flops and 2-to-1 multiplexers with the proposed bidirectional pulsed-latches and non-overlap delayed pulsed clock signals, and by using sub shift-registers and extra temporary storage latches.
Journal ArticleDOI
Novel Low-Complexity and Low-Power Flip-Flop Design
TL;DR: A compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity.
Proceedings ArticleDOI
Design of FIR filter using novel pipelined bypass multiplier
TL;DR: A novel Pipelined architecture of high-speed bypass multiplier which utilizes the bypassing method to minimize the switching activities and incorporates novel pipelining technique for improving its performance is proposed.
Proceedings ArticleDOI
Low Power and High Performance Ring Counter Using Pulsed Latch Technique
Tanushree Doi,Vandana Niranjan +1 more
TL;DR: The performance of ring counter is improved using pulsed latch technique and overall there is an improvement in power delay product.
References
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A 160 MHz 32 b 0.5 W CMOS RISC microprocessor
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TL;DR: This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply and Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board.
Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Proceedings ArticleDOI
Flow-through latch and edge-triggered flip-flop hybrid elements
TL;DR: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.
Journal ArticleDOI
Conditional-capture flip-flop for statistical power reduction
TL;DR: The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power Savings of around 67%, as compared to conventional flip- flops.
Proceedings ArticleDOI
Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers
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TL;DR: An overview of the transmission scheme agreed upon by the IEEE 802.3ab task force for 1 Gb/s full-duplex operation over 4 pairs of category-5 cable is presented and some system level simulation results are presented.