Patent
Method of fabricating field effect transistor having polycrystalline silicon gate junction
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TLDR
In this paper, a polycrystalline silicon gate including the semiconductor junction is formed by implanting ions into the top of the polycrystaline gate simultaneous with implantation of the source and drain regions.Abstract:
A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.read more
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Power semiconductor devices and methods of manufacture
Ashok Challa,Alan Elbanhawy,Thomas E. Grebs,Nathan Kraft,Dean E. Probst,Rodney S. Ridley,Steven Sapp,Qi Wang,Chongman Yun,J.G. Lee,Peter H. Wilson,Joseph A. Yedinak,J.Y. Jung,Hocheol Jang,Babak S. Sani,Richard Stokes,Gary M. Dolny,John Mytych,Becky Losee,Adam Selsley,Robert Herrick,James J. Murphy,Gordon K. Madson,Bruce D. Marchant,Christopher L. Rexer,Christopher Boguslaw Kocon,Debra S. Woolsey +26 more
TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.
Patent
Trench-based power semiconductor devices with increased breakdown voltage characteristics
Joseph A. Yedinak,Ashok Challa +1 more
TL;DR: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed in this article, where the authors present a comparison of different types of power semiconductors with different benefits.
Patent
Methods of making power semiconductor devices with thick bottom oxide layer
Ashok Challa,Alan Elbanhawy,Dean E. Probst,Steven Sapp,Peter H. Wilson,Babak S. Sani,Becky Losee,Robert Herrick,James J. Murphy,Gordon K. Madson,Bruce D. Marchant,Christopher Boguslaw Kocon,Debra S. Woolsey +12 more
TL;DR: In this paper, a conformal oxide film is used to fill the bottom of a trench formed in a semiconductor substrate and cover a top surface of the substrate, and then the oxide film can be etched off the top surface and inside the trench to leave a substantially flat layer of oxide having a target thickness at bottom of the trench.
Patent
Power MOS device with improved gate charge performance
TL;DR: In this article, a double-diffused metal-oxide-semiconductor (DMOS) field effect transistor with an improved gate structure is presented, which includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate.
Patent
Trench-gate ldmos structures
Peter H. Wilson,Steven Sapp +1 more
TL;DR: The TG-LDMOSFET as discussed by the authors provides devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance.
References
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Method for fabricating MOS transistors having gates with different work functions
TL;DR: In this paper, a process for forming an insulated gate field effect transistor (IGFET) with a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types is described.
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