Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects
Ali A. Orouji,M. Jagadesh Kumar +1 more
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TLDR
In this article, the authors present design considerations for a below 100nm channel length SOI MOSFET with electrically induced shallow source/drain junctions and demonstrate that the application of induced source/drain extensions to the SOI mOSFet will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50nm.About:
This article is published in Superlattices and Microstructures.The article was published on 2006-05-01 and is currently open access. It has received 22 citations till now. The article focuses on the topics: Channel length modulation & Short-channel effect.read more
Citations
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A review on performance comparison of advanced MOSFET structures below 45 nm technology node
TL;DR: In this article, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node for analog/RF performance in terms of IOFF, subthreshold performance parameters and DIBL values.
Journal ArticleDOI
Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension
Cong Li,Yiqi Zhuang,Ru Han +2 more
TL;DR: It is demonstrated that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.
Journal ArticleDOI
Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension
Zahra Arefinia,Ali A. Orouji +1 more
TL;DR: In this paper, the authors presented the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism.
Journal ArticleDOI
A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects
Zeinab Ramezani,Ali A. Orouji +1 more
TL;DR: In this paper, a double-gate SOI MOSFET with insulator packets (IPs) at the junction between channel and source/drain (S/D) ends is proposed.
Journal ArticleDOI
Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET
Zeinab Ramezani,Ali A. Orouji +1 more
TL;DR: In this paper, an amended channel doping (ACD) was proposed to improve the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFETs.
References
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Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review
TL;DR: In this paper, the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications is examined.
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Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs
TL;DR: In this article, a 2D analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs).
Journal ArticleDOI
Intrinsic MOSFET parameter fluctuations due to random dopant placement
TL;DR: These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future, and can be reduced to some degree by selecting optimal values of channel width.
Journal ArticleDOI
1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints
TL;DR: In this paper, an approach for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions was described. But the approach was not followed in determining the room-temperature and the 77 K hotelectron limited voltages of a device designed to have a minimum channel length.
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A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation
TL;DR: In this article, the authors presented the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET.
Related Papers (5)
Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions
A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects
Zeinab Ramezani,Ali A. Orouji +1 more