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Journal ArticleDOI

Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory

TLDR
The basic architecture of the Neurocube is presented and an analysis of the logic tier synthesized in 28nm and 15nm process technologies are presented and the performance is evaluated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.
Abstract
This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.

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Proceedings ArticleDOI

Multi-Layer In-Memory Processing

TL;DR: By introducing concurrent task scheduling to MLIMP, this paper achieves improved performance and energy efficiency for graph neural networks and multiprogramming of data parallel applications.
Posted Content

SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM.

TL;DR: SIMDRAM as discussed by the authors is a general-purpose processing-using-DRAM framework that enables the efficient implementation of complex operations, and provides a flexible mechanism to support the implementation of arbitrary user-defined operations.
Proceedings ArticleDOI

Socrates-D 2.0: A Low Power High Throughput Architecture for Deep Network Training

TL;DR: This paper presents a processor design, Socrates-D 2.0, a multicore architecture for deep neural network based training and inference, which consists of a set of processing cores, each with internal memories to store synaptic weights.
Patent

System and method for in-memory compute

TL;DR: In this article, an in-memory computation system is described, which includes a dynamic random access memory (DRAM) module and a memory controller configured to violate a timing specification for the DRAM module.
Proceedings ArticleDOI

NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures

TL;DR: NeuroPIM as mentioned in this paper uses a neural network as the memory-side general-purpose accelerator, which is mainly motivated by the observation that in many real-world applications, some program regions, or even the entire program, can be replaced by neural network that is learned to approximate the program's output.
References
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GradientBased Learning Applied to Document Recognition

TL;DR: Various methods applied to handwritten character recognition are reviewed and compared and Convolutional Neural Networks, that are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques.
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