Journal ArticleDOI
Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory
Duckhwan Kim,Jaeha Kung,Sek M. Chai,Sudhakar Yalamanchili,Saibal Mukhopadhyay +4 more
- Vol. 44, Iss: 3, pp 380-392
TLDR
The basic architecture of the Neurocube is presented and an analysis of the logic tier synthesized in 28nm and 15nm process technologies are presented and the performance is evaluated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.Abstract:
This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.read more
Citations
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Journal ArticleDOI
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
TL;DR: In this article , an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface is presented.
Proceedings ArticleDOI
MetaNMP: Leveraging Cartesian-Like Product to Accelerate HGNNs with Near-Memory Processing
TL;DR: MetaNMP as mentioned in this paper proposes a cartesian-like product paradigm to generate all metapath instances on the fly for heterogeneous graphs, and then designs a data flow for aggregating vertex features on metAPath instances, which aggregates vertex features along the direction of the metAP instances dispersed from the starting vertex to exploit shareable aggregation computations.
Posted Content
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic
Mahdi Nazemi,Arash Fayyazi,Amirhossein Esmaili,Atharva Khare,Soheil Nazar Shahsavani,Massoud Pedram +5 more
TL;DR: In this paper, the authors present NullaNet Tiny, an across-the-stack design and optimization framework for constructing resource and energy-efficient, ultra-low-latency FPGA-based neural network accelerators.
Journal ArticleDOI
A survey of architectures of neural network accelerators
TL;DR: This survey will introduce some architecture designs of typical accelerators, including the computing unit, data flow, the characteristics of the different neural networks to be accelerated, and design considerations on emerging platforms, etc.
Journal ArticleDOI
Speeding-up neuromorphic computation for neural networks: Structure optimization approach
Heechun Park,Taewhan Kim +1 more
TL;DR: This work proposes a new neuromorphic computing architecture of mixing both dendritic and axonal-based neuromorphic cores in a way to totally eliminate the inherent non-zero waiting time between neuromorph cores to speed up the computation of fully connected neural network twice as fast as that of the existing architectures.
References
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Yann LeCun,Léon Bottou,Léon Bottou,Yoshua Bengio,Yoshua Bengio,Yoshua Bengio,Patrick Haffner +6 more
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GradientBased Learning Applied to Document Recognition
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TL;DR: Various methods applied to handwritten character recognition are reviewed and compared and Convolutional Neural Networks, that are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques.
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