Proceedings ArticleDOI
Organic Computing at the System on Chip Level
A. Bouajila,J. Zeppenfeld,Walter Stechele,Andreas Herkersdorf,Andreas Bernauer,Oliver Bringmann,Wolfgang Rosenstiel +6 more
- pp 338-341
TLDR
This paper presents an organic computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques.Abstract:
The evolution of CMOS technologies leads to integrated circuits with ever smaller device sizes, lower supply voltage, higher clock frequency and more process variability. Intermittent faults effecting logic and timing are becoming a major challenge for future integrated circuit designs. This paper presents an Organic Computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques. We demonstrate the feasibility of this approach by example on the processing pipeline of a public-domain RISC CPU core.read more
Citations
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Proceedings ArticleDOI
A Specification and Construction Paradigm for Organic Computing Systems
TL;DR: The core idea is that the behaviour of an organic computing system can be split into productive phases and self-x phases, which allows for a generic description of how ``organic'' aspects can be specified and implemented.
Journal ArticleDOI
Self-Awareness in Systems on Chip— A Survey
TL;DR: This paper presents an overview centered around the paradigm of self-awareness in computing systems, which helps systems to understand, manage, and report on their own system behavior.
Learning Classifier Tables for Autonomic Systems on Chip.
TL;DR: This paper introduces a new hardware-based machine learning building block – called Learning Classifier Table (LCT) – for the run-time reliability, performance and power optimization of future generations of Systems-on-Chip.
Journal ArticleDOI
Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption
TL;DR: SMART was evaluated using a Sobel edge-detection application and was shown to tolerate stressful sequences of injected transient and permanent faults while reducing dynamic power consumption by 30% compared to conventional triple modular redundancy techniques, with nominal impact on the fault-tolerance capabilities.
Book ChapterDOI
A reference architecture for self-organizing service-oriented computing
TL;DR: This paper proposes a reference architecture to establish controlled self-organization in a service-oriented environment with respect to existing reference architectures for SOC and self- Organization.
References
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