Journal ArticleDOI
Pulsed current-mode signaling for nearly speed-of-light intrachip communication
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In this article, the authors describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency, where the effect of wire inductance is maximized, allowing the onchip wires to function as transmission lines with considerably reduced dispersion.Abstract:
In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18-/spl mu/m CMOS process is described and measured.read more
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Journal ArticleDOI
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
Amlan Ganguly,Kevin Chang,Sujay Deb,Partha Pratim Pande,Benjamin J. Belzer,Christof Teuscher +5 more
TL;DR: It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude.
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution
TL;DR: New techniques for logic circuits and interconnect, for memory, and for clock and power distribution are discussed, and the role of geometrically regular circuits as one promising solution is discussed.
Journal ArticleDOI
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS
TL;DR: In this article, the authors present a survey of recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.
Proceedings ArticleDOI
High-Speed and Low-Energy Capacitively-Driven On-Chip Wires
TL;DR: The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers.
Journal ArticleDOI
High Speed and Low Energy Capacitively Driven On-Chip Wires
TL;DR: The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers.
References
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Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Journal ArticleDOI
The future of wires
R. Ho,Ken Mai,Mark Horowitz +2 more
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Book
Digital and analog communication systems
TL;DR: This book provides a broad introduction to basic analog and digital principles and their application to the design and analysis of real- world communication systems and provides readers with a working knowledge of how to use both classical mathematical and personal computer methods to analyze, design, and simulate modern communication systems.
Journal ArticleDOI
Low-jitter and process independent DLL and PLL based on self biased techniques
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.