Journal ArticleDOI
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test
Chao-Wen Tzeng,Shi-Yu Huang +1 more
TLDR
This paper presents an X-fill scheme that properly utilizes the don't-care bits in test patterns to simultaneously reduce the test time as well as the test power (including both capture power and shifting power).Abstract:
This paper presents an X-fill scheme that properly utilizes the don't-care bits in test patterns to simultaneously reduce the test time as well as the test power (including both capture power and shifting power). This scheme, called Quick-and-Cool X-fill (QC-Fill), built upon the multicasting-based scan architecture, further leverages on the merits of previous low-capture-power X-fill methods through techniques like multicasting-driven X-fill and clique stripping. QC-Fill is independent of the automatic test pattern generation patterns and does not require any extra area overhead. Experimental results demonstrate that this scheme strikes a good balance between the seemingly conflicting criteria of low power and test compression.read more
Citations
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Proceedings ArticleDOI
Low power compression utilizing clock-gating
TL;DR: Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.
Journal ArticleDOI
Low-Power Test Generation by Merging of Functional Broadside Test Cubes
TL;DR: Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and nonfunctional) broadside tests in benchmark circuits.
Proceedings ArticleDOI
Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity
TL;DR: A procedure is described that generates broadside test sets with bounded switching activity during fast functional capture cycles based on the maximum switching activity of a functional broadsideTest set, targeting transition faults in full-scan circuits.
Proceedings ArticleDOI
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating
TL;DR: A method to simultaneously reduce test data volume and test power in atspeeddelay test utilizing clock gating is presented, achieved through not clocking a high proportion of scan chains during both scan shift and test response capture.
Journal ArticleDOI
Test Pattern Modification for Average IR-Drop Reduction
TL;DR: A novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern with almost no fault coverage loss and no test pattern inflation is presented.
References
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Journal ArticleDOI
Survey of low-power testing of VLSI circuits
TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Proceedings ArticleDOI
Static compaction techniques to control scan vector power dissipation
TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Proceedings ArticleDOI
Minimizing power consumption in scan testing: pattern generation and DFT techniques
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.