Open AccessDOI
Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose
Sharareh Zamanzadeh,Ali Jahanian +1 more
- Vol. 8, Iss: 1, pp 53-60
TLDR
This paper presented a “Self Authentication” methodology in which the originality of sub-components in bitstream is authenticated in parallel with the intrinsic operation of the design, which considerably improves the IP security against malicious updates with reasonable overheads.Abstract:
FPGA platforms have been widely used in many modern digital applications due to their low prototyping cost, short time-to-market and flexibility. Field-programmability of FPGA bitstream has made it as a flexible and easy-to-use platform. However, access to bitstream degraded the security of FPGA IPs because there is no efficient method to authenticate the originality of bitstream by the FPGA programmer. The issue of secure transmission of configuration information to the FPGAs is of paramount importance to both users and IP providers. In this paper we presented a "Self Authentication" methodology in which the originality of sub-components in bitstream is authenticated in parallel with the intrinsic operation of the design. In the case of discovering violation, the normal data flow is obfuscated and the circuit would be locked. Experimental results show that this methodology considerably improves the IP security against malicious updates with reasonable overheads.read more
References
More filters
Journal ArticleDOI
Fault Analysis-Based Logic Encryption
Jeyavijayan Rajendran,Huan Zhang,Chi Zhang,Garrett S. Rose,Youngok Pino,Ozgur Sinanoglu,Ramesh Karri +6 more
TL;DR: This work relates logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique that enables a designer to controllably corrupt the outputs.
Journal ArticleDOI
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Jason Luu,Jeffrey Goeders,Michael Wainberg,Andrew Somerville,Thien Yu,Konstantin Nasartschuk,Miad Nasr,Sen Wang,Tim X. Liu,Nooruddin Ahmed,Kenneth B. Kent,Jason H. Anderson,Jonathan Rose,Vaughn Betz +13 more
TL;DR: Recent advances in the open source Verilog-to-Routing (VTR) CAD flow are described that enable further research in these areas and release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments.
Proceedings ArticleDOI
From the bitstream to the netlist
TL;DR: This work aims to raise awareness about security issues for users of FPGAs and makes custom compilation and low-level tinkering with bitstreams - à la JBits - possible.
Journal ArticleDOI
FPGA Security: Motivations, Features, and Applications
TL;DR: Motivated by specific threats, this paper describes FPGA security primitives from multiple FPGAs vendors and gives examples of those primitives in use in applications.
Journal ArticleDOI
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream
TL;DR: This work has demonstrated the feasibility of hardware Trojan insertion in circuits mapped on FPGAs by direct modification of the FPGA configuration bitstream by a software program to insert a hardware Trojan in the design.