Journal ArticleDOI
Sub-10 nm imprint lithography and applications
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TLDR
A new lithography paradigm that is based on deformation of a resist by compression molding rather than altering its chemical structure by radiation, and is designed to fabricate nanostructures inexpensively with high throughput is presented.Abstract:
New developments, further details, and applications of imprint lithography are presented. Arrays of 10 nm diameter and 40 nm period holes were imprinted not only in polymethylmethacrylate (PMMA) on silicon, but also in PMMA on gold substrates. The smallest hole diameter imprinted in PMMA is 6 nm. All the PMMA patterns were transferred to a metal using a liftoff. In addition, PMMA mesa’s of a size from 45 nm to 50 μm were obtained in a single imprint. Moreover, imprint lithography was used to fabricate the silicon quantum dot, wire, and ring transistors, which showed the same behavior as those fabricated using electron (e)-beam lithography. Finally, imprint lithography was used to fabricate nanocompact disks with 10 nm features and 400 Gbits/in.2 data density—near three orders of magnitude higher than current critical dimensions (CDs). A silicon scanning probe was used to read back the data successfully. The study of wear indicates that due to the ultrasmall force in tapping mode, both the nano-CD and the ...read more
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References
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Journal ArticleDOI
Single Charge Tunneling: Coulomb Blockade Phenomena in Nanostructures
TL;DR: Averin et al. as discussed by the authors proposed a single charge tunneling method to transfer electrons one-by-one in low-Capacitance tunnel junctions, and applied it to semiconductor nanostructures.