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Journal ArticleDOI

The “barrier mode” behaviour of a junction FET at low drain currents

R.J. Brewer
- 01 Nov 1975 - 
- Vol. 18, Iss: 11, pp 1013-1017
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TLDR
In this paper, the behavior of a junction FET with a gate-source reverse bias exceeding the pinch-off voltage is discussed, and it is seen that both the transfer and output characteristics have an exponential character, and this is attributed to the presence of a potential barrier between the source and drain.
Abstract
The behaviour of a junction FET with a gate-source reverse bias exceeding the pinch-off voltage is discussed. It is seen that both the transfer and output characteristics have an exponential character, and this is attributed to the presence of a potential barrier between the source and drain. Simple expressions are given for both the conductance and transconductance in terms of parameters which, in the case of long gate devices, may be evaluated analytically, or, in the case of short gate devices, evaluated numerically using a relatively simple computer model.

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Citations
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Journal ArticleDOI

GaAs LSI-directed MESFET's with self-aligned implantation for n + -layer technology (SAINT)

TL;DR: In this paper, self-aligned implantation for n+layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's.
Journal ArticleDOI

A first-order theory of the static induction transistor

C. Bulucea, +1 more
TL;DR: In this paper, a first-order theory of the static induction transistor (SIT) is proposed, which provides a unitary analytical description of its characteristics over the full range of normally encountered biasing conditions.
Journal ArticleDOI

On the very-high-current degradations on Si n-p-n transistors

TL;DR: In this paper, the emitter contact does not fail abruptly; rather, its contact resistance drifts gradually, and the drift in emitter resistance can be thermally accelerated and is consistent with the electromigration phenomenon.
Journal ArticleDOI

Two-dimensional particle modeling of submicrometer gate GaAs FET's near pinchoff

TL;DR: In this article, the characteristics of very short gate GaAs MESFET's have been studied using a particle model which takes into account the hot-electron transport phenomena, i.e., the velocity overshoot.
Journal ArticleDOI

Short-channel effects and drain-induced barrier lowering in nanometer-scale GaAs MESFET's

TL;DR: In this article, the authors investigated short-channel effects in GaAs MESFETs with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers.
References
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Journal ArticleDOI

Low level currents in insulated gate field effect transistors

TL;DR: In this paper, a theory for low-level current operation in insulated gate field effect transistors is developed using the depletion approximation for the semiconductor surface potential, and an analytical expression is obtained which is accurate for gate voltages corresponding to surface operation from depletion to the onset of strong inversion.
Journal ArticleDOI

Subthreshold design considerations for insulated gate field-effect transistors

TL;DR: In this article, the effect of drain voltage on the sub-threshold region as the channel length becomes shorter and the impact of substrate bias on both the shift in and the slope of the subthreshold curves is discussed.
Journal ArticleDOI

An analysis of current saturation mechanism of junction field-effect transistors

TL;DR: In this paper, a two-dimensional numerical analysis for junction field-effect transistors with small and large values of length-to-width ratio is presented, where the effects of the geometry of the device and the field dependent mobility to the drain characteristics are clarified.
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