Showing papers on "Adder published in 1989"

Log-polar signal processing

Abstract: The invention relates to a method and an arrangement intended for radio communication systems and effective in digitalizing and subsequently processing numerically arbitrary radio signals. The signals are represented by composite (complex) vectors which have been subjected to disturbances in the system, such that information in the signals has been lost. This information is restored in its entirety when practising the present invention. For the purpose of solving this problem, the inventive digitalizing arrangement includes a multistage logarithmic amplifier chain (A) in which each stage is connected to a separate detector (D), the output signals of which are added in an adder. The adder output signals are then transmitted to a first A/D-converter (AD1) for digitalizing and converting the amplitude components of the signal. At the same time, the undetected signal from the saturated output stage in the amplifier chain is transmitted to a second A/D-converter for digitalizing and converting the phase components of the signal. The digital values obtained on the outputs of the AD-converters (AD1, AD2) are applied to different inputs of a digital signal processor (MP) for numerical processing of the pairwise received digital values in a manner such as to restore the complete vector characteristic of the signal.

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

Abstract: A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >

Subsampling time-domain digital filter using sparsely clocked output latch

Abstract: The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.

Ultrafast compact 32-bit CMOS adders in multiple-output domino logic

Abstract: A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In this logic style, single logic gates produce multiple functions, and a circuit's device count can be reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In addition, MODL circuits are, by construction, considerably more stable than other dynamic circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces the adder's worst-case path by two logic stages has also been devised. This CLA structure has been developed to effectively utilize the advantages of MODL. Taken together, these developments have resulted in two 32-bit CMOS adders, providing area and speed improvements of 1.5* and 1.7* over the combination of the domino and conventional CLA techniques. Both adders have been fabricated in a standard 0.9- mu m two-level metal CMOS technology, and measured results show that the straight adder has achieved 32-bit addition times of less than 3.1 ns at 25 degrees C with V/sub DD/+5.0 V. >

Optimal group distribution in carry-skip adders

Abstract: The carry-skip adder, because of its greater topological regularity and layout simplicity, is considered a good compromise in terms of area and performance. Some general rules have been suggested for its design, but they tend to overlook many important implementation details and cannot be applied to carry-skip adders with more than two levels of carry-skip or with different delays in the carry paths. The result is a nonoptimal distribution of groups and subgroups of the carry-skip circuits, degrading the worst-case delay of the adder. A new algorithm for determining the optimal distribution with no restriction on the number of skip levels is presented. Some results and conclusions are presented regularly in the realization of such an adder in bipolar ECL technology. >

Electrical power control apparatus and methods

Abstract: Electrosurgery apparatus includes an r.f. power amplifier with an output to a patient electrode. The amplifier is controlled by the voltage of input signals from a control unit which receives a sample of the voltage and current of the output signal. The voltage and current signals are supplied to A/D converters to provide two digital signals that are used to address a look-up table in an EPROM and provide a digital output representative of impedance. A switch is set by the user to the desired mode/power curve and this provides a digital signal which together with the impedance signal is used to address a second look-up table in an EPROM which contains digital representations of the required output voltage of the amplifier to produce the desired power level. An adder compares the required voltage with a feedback of the actual voltage to produce an error signal that is supplied to the amplifier to control its output.

RBCD: redundant binary coded decimal adder

Abstract: The major advantage of the binary coded decimal (BCD) system is in providing rapid binary-decimal conversion. The shortcoming of the BCD system is that BCD arithmetic operations are often slow and require complex hardware. The performance of BCD operations can be improved through a redundant binary coded decimal (RBCD) representation which leads to carry-free operations. This paper introduces the VLSI design of an RBCD adder. The design consists of two small PLAs and two 40-bit binary adders for one digit of the RBCD adder. The addition delay is constant for n-digit RBCD addition (no carry propagation delay). The VLSI time and space complexities of the design as well as its layout are presented. In addition, the authors show that BCD to RBCD conversion can be carried out in a constant time. However, RBCD to BCD conversion requires a carry-ripple operation which can be accomplished with a complexity equivalent to that of the carry-look-ahead circuitry.< >

Arc-welding monitor

Abstract: The arc-welding monitor has a weld power supply, units for generating signals proportional to welding current and voltage, an audio-signal generator, welding current and voltage comparators and a monitoring sequence logic analyzer having a signal switch responsive to variations of monitored quantities, which is connected to the outputs of said welding current and voltage comparators, a signal switch responsive to incremental changes in monitored parameters, and welding current and voltage adders. One input of each adder is connected to the outputs of said units for generating signals proportional to welding current and voltage, respectively, while the second input of each adder is combined with the input of the corresponding comparator, the outputs thereof being connected to the inputs of the signal switch responsive to incremental changes in monitored parameters.

One clock address pipelining in segmentation unit

Abstract: A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.

Photoelectric conversion device

Abstract: PURPOSE:To improve a frequency characteristic, to heighten the peak value of a signal and also, to perform a fast operation, and to improve an S/N by damping a noise by providing a low-input impedance amplifier and a non- inversion input signal adder, etc CONSTITUTION:The low-input impedance amplifier AMPA inputs signals from photoelectric converter blocks B1 and B2, etc, and outputs a sharp signal with a high peak value Next, the output signal of each block, after being added by the non-inversion input signal adder SUMp(odd block addition) and the non-inversion input signal adder SUMn(even block addition), is inputted to a differential amplifier AMPB of high CMRR The amplifier B damps in-phase signals (or noises) being inputted to inputs of (+) and (-), respectively, and amplifies a differential signal In other words, since the signal generated by each photoelectric converter S is amplified as the differential signal, it is possible to improve the frequency characteristic of a detection system, and to heighten the peak value and also, to perform the fast operation and to improve the S/N by damping the noise

Compression and expansion technique for digital audio data

Abstract: A compression and expansion apparatus and method for compressing and expanding digital audio signals using adaptive differential pulse-coding-modulation for high fidelity music is described. The apparatus comprises a predictor, a first and second adder, a first and second adjuster, a quantizer, an inverse quantizer and a step-size adaptor. An input digital signal and predicted signal are added by the first adder, producing the difference between the two signals. The output of the first adder is coupled to the first adjuster which acts as a multiplier to alter the gain and normalize the signal. The signal is then quantized by the quantizer. The output of the quantizer is sent to both the inverse quantizer and the adaptor. The adaptor acts like an automatic-gain-control to control the gain provided by the first adjuster. After inverse quantization by the inverse quantizer, the signal is sent to the second adjuster to remove the effects of the first adjuster process, i.e. denormalize and remove gain. Then the signal is sent to the second adder to add back in the predicted signal removed by the first adder. Next the signal is outputted and sent to the predictor. The predictor uses the output signal to prepare another predicted signal for a subsequently inputted digital signal. Wherein, an inputted digital audio signal and a corresponding outputted digital audio signal are substantially similar.

All-digital quadrature modulator

Abstract: A CPFSK quadrature modulator (300) is disclosed utilizing an all-digital implementation. The serial data input signal (20 ) is formatted into parallel overlapping bits using a shift register (202), an up/down counter (206), and an interpolation counter (204) and applied as address lines to in-phase and quadrature-phase memories (208, 210). A multiple of the bit clock is used to address carrier generation ROMs (216, 218). The carrier signal is then modulated by the in-phase and quadrature-phase data signals (212, 214, 222), converted to an analog signal by a D/A converter (250), and low pass filtered (254) to generate the analog output signal (255). A single ROM (440) is utilized to implement all the look-up tables, multipliers, and adder. The all-digital implementation allows for precise control of the modulation index to h═0.5±0.05 percent over time, temperature, power levels, etc.

Method and apparatus for shared radix 4 division and radix 4 square root

Abstract: An improved logic structure and a method for implementing the same to perform division and square-root operations for radix four and higher is disclosed. The divsion and square-root bits are generated by a non-restoring method with the partial remainder, partial radicand, quotient and root all in redundant form. The partial remainder/radicand is stored in a series of sum and carry registers. The upper bits from these registers are supplied to a carry look-ahead adder for conversion to non-redundant form. These upper bits are then used to select a next divisor or root from a prediction programmable logic array (PLA). The output of the prediction PLA is supplied to a quotient/root register and a divisor/root multiple selector. The output of the selector is supplied to a carry save adder which has its output provided back to the input of the partial remainder/radicand sum and carry registers. The system of the present invention allows both division and square root calculations to be done with the same hardware. The square-root algorithm requires an initial look-up PLA for determining the initial bits of the square-root. Logic is provided for coupling the output of this initial look-up PLA to the quotient/root register and divisor/root multiple select during the first few iterations.

Multiprocessor implementation of 2-D denominator-separable digital filters for real-time processing

Abstract: The problem of realizing 2-D denominator-separable digital filters is considered. Four realizations are derived with emphasis on real-time processing in a multiprocessor environment. This implies maximizing parallelism and pipelining, minimizing data throughput delay, and developing computational primitives which can be used as building blocks for very-large-scale integrated-circuit (VLSI) implementation. Advantage is taken of well-known realization structures for 1-D systems in developing the derivations. The performance of each realization is evaluated using criteria appropriate for real-time processing and multiprocessor implementation. It is shown that a simple computational primitive of one multiplier and one adder can be used to realize the filter with data throughput delay time equal to the time required for one multiplication and one addition, independent of the order of the filter. However, the number of required processors is different for each realization, and thus each realization has a different efficiency measure. >

Individual identification apparatus

Abstract: An apparatus for identifying an individual includes a reader (7, 25) for reading the input image of a finger (9) of the individual and producing an image signal corresponding to the image of the finger, an adder (23) for adding the image signal output from the reader (7, 25) in a direction perpendicular to a longitudinal direction of the finger and outputting an addition signal, and a memory such as an IC card (33) for storing a previously registered addition signal output from the adder (23). A first signal obtained by regular sampling of the current addition signal from the adder (23) and a second signal obtained by corresponding sampling of the addition signal stored in the IC card (33) are used to generate a coarse position alignment. After the coarse position alignment, the actual current addition signal and the actual stored addition signal are used without sampling to generate a fine position alignment. The two addition signals are then compared to decide whether the finger image corresponds to that of an authorised person.

Polarization-encoded optical shadow-casting: direct implementation of a carry-free adder.

Abstract: Carry-free addition based on the redundant binary number system is adopted for the lensless polarization-encoded optical shadow-casting (POSC) system. A carry-free POSC adder is designed by determining the codings of (1) the redundant input bits for generating the intermediate sum and intermediate carry and (2) the intermediate sum and intermediate carry for generating the carry-free sum.

Merged CMOS/bipolar current switch logic (MCSL)

Abstract: A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-bit BiCMOS full adder was measured. This is about five times faster than an optimized CMOS adder. >

Circuit for adding/subtracting two floating point operands

Abstract: In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa not to be normalized. A dual adder scheme is used to always provide a normalized result. One adder provides an unshifted result while the second adder provides a shifted result. A logic circuit looks for a carry out when performing addition and a bit value of the msb when performing subtraction to select the output from the adder providing the proper normalization. Rounding logic circuitry is used to predict the rounding of the resultant mantissa and carry bits are coupled as a carry-in to the adders to achieve the proper rounding in the same clock cycle as the adding/subtracting of the two mantissas.

Binary counter with counting period of one half adder independent of counter size

Abstract: The properties that make a fast counter suitable for many applications are: (1) a high counting rate, independent of the counter size; (2) a binary output that can be read on-the-fly; (3) a sampling rate equal to the counting rate; and (4) a regular implementation suitable for VLSI. The authors describe the implementation of a counter having these properties. The minimum period of the counter is equal to the delay of one half adder plus the delay of loading a flip-flop. Both a modulo-2/sup n/ case and the more general modulo-p cases are considered. >

Fuzzy inference apparatus

Abstract: A fuzzy inference engine has a plurality of individual inference sections and a concluder section for integrally processing outputs from the inference sections. In order to simplify the fuzzy inference engine, nonfuzzy output is obtained through a simple arithmetic operation. Each fuzzy inference section comprises at least one membership function circuit and a predetermined operation circuit. A setting element sets the center position of a membership function of a consequent of each rule. A multiplier multiplies a value from the predetermined operation circuit by the center position from the setting element. A first adder sums the resulting product for each inference first adder by the values from theb section. A second adder sums the values from the predetermined operation circuit for each inference section. A divider divides the values from the second adder to produce the nonfuzzy output. As an option, and additional multiplier multiplies the output from the predetermined operation circuit by a coefficient.

Probabilistic inference gate

Abstract: The present system performs linear transformations on input probabilities and produces outputs which indicate the likelihood of one or more events. The transformation performed is a product of linear transforms such as P o =[A j P j +B j ]·[A k P k +B k ] where P j and P k are input probabilities, P o is an output event probability and A j , B j , A k and B k are transformation constants. The system includes a basic processing unit or computational unit which performs a probabilistic gate operation to convert two input probability signals into one output probability signal where the output probability is equal to the product of linear transformations of the input probabilities. By appropriate selection of transformation constants logical and probabilistic gates performing the functions of AND, NAND, OR, NOR, XOR, NOT, IMPLIES and NOT IMPLIES can be created. The basic unit can include three multipliers and two adders if a discrete component hardwired version is needed for speed or a single multiplier/adder, associated storage and multiplex circuits can be used to accomplish the functions of the hardwired version for economy. This basic unit can also be provided as a software implementation, can be implemented as a hardwired decision tree element implementation or implemented as a universal probabilistic processor and provided with a bus communication structure to create expert systems or neural networks suitable for specific tasks. The basic units can be combined to produce a virtual basic building block which has more virtual processors than physical processors to improve processor utilization. The building blocks can be combined into an array to produce either a high speed expert system or a high speed neural network.

TCAD: a 27 MHz 8*8 discrete cosine transform chip

Abstract: The circuit performs two-dimensional forward and inverse discrete cosine transform (DCT) on 8*8 blocks of data. Its implementation is based on the row-column decomposition scheme. A memory look-up approach combined with bit-serial structures is used to compute each one-dimensional DCT. A register-based transposition stage maintains the serial representation of the data after the first one-dimensional transform. This 50000-transistor circuit only uses read-only memories, registers, and adders. A pipeline architecture and a very regular layout lead to high-speed performances up to digital TV rates. The 32-pin version of the circuit accepts 9-bit pixel input and produces 12-bit coefficients in forward mode and vice-versa for inverse DCT mode. Its area is 26 mm/sup 2/ for a 1.2- mu m CMOS technology. >

A single-chip 16-bit 25-ns real-time video/image signal processor

Abstract: A single-chip real-time video/image processor (VISP) has been developed that integrates functions based on a variable seven-stage pipeline arithmetic architecture in a 16-bit fixed-point data format. A three-input adder implemented in complementary CMOS reduced-swing logic, which is twice as fast as conventional CMOS logic, achieving a 25-ns instruction cycle, is shown. Single-VISP processing times are: edge detection (3*3 Laplacian), 14.8 ms; distance calculation, 1.7 ms; temporal filtering (1-tap IR), 5.0 ms; linear quantization, 3.3 ms; and 3/5*3/5 picture reduction (separate 5-tap FIR), 5.9 ms. An example is shown of a two-dimensional discrete cosine transformation which requires 26.3 ms to execute with one VISP when 256*256 pixel processing at a 25-ns instruction cycle is employed. >

Programmable digital filter

Abstract: The digital filter comprises a plurality of parallel adders (20...24), each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element (30...34). The second input of each adder is connected in parallel to the output of one of a plurality of memory banks (40...44), each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.

A restructurable VLSI robotics vector processor architecture for real-time control

Abstract: The authors propose a restructurable architecture based on a VLSI robotics vector processor (RVP) chip. It is specially tailored to exploit parallelism in the low-level matrix/vector operations characteristic of the kinematics and dynamics computations required for real-time control. The RVP is composed of three tightly synchronized 32-bit floating-point processors to provide adequate computational power. Besides adder and multiplier units in each processor, the RVP contains a triple register-file, dual shift network, and dual high-speed input/output (I/O) channels to satisfy the storage and data movement demands of the computations targeted. Efficiently synchronized multiple-RVP configurations, which may be viewed as variable very-long-instruction-word architectures, can be constructed and adapted to match the computational requirements of specific robotics computations. The use of the RVP is illustrated through a detailed example of the Jacobian computation, demonstrating good speedup over conventional microprocessors even with a single RVP. The RVP has been developed to be implementable on a single VLSI chip using 1.2- mu m CMOS technology, so that a single-board multiple-RVP system can be targeted for use on a mobile robot. >

Absolute value calculating circuit having a single adder

Abstract: An absolute value calculating circuit for producing an absolute value of the difference between first and second numerical values. The circuit includes a first inverter for inverting the first numerical value, a first adder for adding the inverted first numerical value and the second numerical value, and a second inverter for inverting the output of the first adder. The circiuit further includes a second adder for adding 1 to the output of the adder and a selector for selecting and outputting, as the absolute value of the difference between the first and second numerical values, either the inverted output of the first adder or the output of the second adder in accordance with a sign of the output of the first adder.

A 15 ns 32atimes;32-bit CMOS multiplier with an improved parallel structure

Abstract: A 32-bitt32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-mm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68t2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation

Recursive equations for hardwired binary adders

Abstract: A sum equation for the implementation of parallel hardwired binary adders is introduced. It is suggested that the proposed sum equation, when compared with Ling's high-speed sum, will result in some advantages, and that it can be used in the design of high-speed parallel adders using generally available technologies. It is shown that a 32-bit adder can be designed in three stages using 3 × 8 AND-ORs, 3 × 4 AND-OR-INVERTs and 2 × 4 OR-ANDs CMOS gates, and that a bipolar adder can be designed in four stages, with three-way NANDs and eight-way AND-dotting. In addition, it is suggested that a three-stage 32-bit adder using NANDs and AND-dotting is most likely unrealistic. The paper also describes the design of a number of adders, and discusses the speed, feasibility and complexity of their design.

Dual-tone direct digital synthesizer

Abstract: Arrangements are provided for generation of dual-tone waveforms utilizing direct digital waveform synthesis techniques and architecture and retaining the advantageous characteristics of direct digital waveform synthesis. Preferred embodiments feature combination of generated waveforms at an analog adder, a digital adder using a single digital-to-analog converter and at a single wave table, respectively, each providing particular hardware economies and operational advantages with respect to other preferred embodiments.

Digital control system

Abstract: A digital controller comprising a deviation calculator, a positional P-controlling calculation device, a velocity-type I-controlling calculation device, a signal converter, and an adder unit The deviation calculator for subtracts a process variable of an object from a set point variable, to obtain a deviation The positional P-controlling calculation device performs positional P-calculation on the deviation obtained by the deviation calculator The velocity-type I-controlling calculation device performs velocity-type I-calculation on the deviation The signal-converting device converts the velocity-type I-calculation output of the velocity-type I-controlling algorithm device, into a positional I-signal The adder unit adds the positional I-signal obtained by the signal-converting device and the positional P-calculation output obtained by the positional P-controlling algorithm device, thereby obtaining a manipulative variable The manipulative variable value is supplied to the object to control the object