Showing papers on "Boolean function published in 1996"

Improving the variable ordering of OBDDs is NP-complete

Abstract: Ordered binary decision diagrams are a useful representation of Boolean functions, if a good variable ordering is known. Variable orderings are computed by heuristic algorithms and then improved with local search and simulated annealing algorithms. This approach is based on the conjecture that the following problem is NP-complete. Given an OBDD G representing f and a size bound s, does there exist an OBDD G* (respecting an arbitrary variable ordering) representing f with at most s nodes? This conjecture is proved.

Model checking large software specifications

Abstract: In this paper we present our results and experiences of using symbolic model checking to study the specification of an aircraft collision avoidance system. Symbolic model checking has been highly successful when applied to hardware systems. We are interested in the question of whether or not model checking techniques can be applied to large software specifications.To investigate this, we translated a portion of the finite-state requirements specification of TCAS II (Traffic Alert and Collision Avoidance System) into a form accepted by a model checker (SMV). We successfully used the model checker to investigate a number of dynamic properties of the system.We report on our experiences, describing our approach to translating the specification to the SMV language and our methods for achieving acceptable performance in model checking, and giving a summary of the properties that we were able to check. We consider the paper as a data point that provides reason for optimism about the potential for successful application of model checking to software systems. In addition, our experiences provide a basis for characterizing features that would be especially suitable for model checkers built specifically for analyzing software systems.The intent of this paper is to evaluate symbolic model checking of state-machine based specifications, not to evaluate the TCAS II specification. We used a preliminary version of the specification, the version 6.00, dated March, 1993, in our study. We did not have access to later versions, so we do not know if the properties identified here are present in later versions.

Combinational logic synthesis for LUT based field programmable gate arrays

Abstract: The increasing popularity of the field programmable gate-array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA-specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K-input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic techniques. A comprehensive list of references is compiled in the attached bibliography.

Principles of Digital Design

Abstract: (NOTE: Each chapter ends with a summary, problems and further readings.) 1. Introduction. Design representation. Levels of abstraction. Design process. CAD tools. Typical design process. Road map. 2. Data Types and Representations. Positional number systems. Octal and hexadecimal numbers. Number system conversions. Addition and subtraction of binary numbers. Representation of negative numbers. Two's-complement addition and subtraction. Binary ultiplication. Binary division. Floating-point number representation. Binary codes for decimal numbers. Character codes. Codes for error detection and correction. Hamming codes. 3. Boolean Algebra and Logic Design. Algebraic properties. Axiomatic definition of boolean algebra. Basic theorems of boolean algebra. Boolean functions. Canonical forms. Standard forms. Digital logic gates. Extension to multiple inputs and multiple operators. Gate implementations. VLSI technology. 4. Simplification of Boolean Functions. The map representation. The map method of simplification. Don't-care conditions. The tabulation method. Technology mapping for gate arrays. Technology mapping for custom libraries. Hazard-free design. 5. Combinatorial Components. Carry-ripple adders. Carry-look-ahead adders. Adders/subtractors. Logic unit. Arithmetic-Logic Unit. Decoders. Selectors. Buses. Priority encoders. Magnitude comparators. Shifters and rotators. Read-Only memories. Programmable logic arrays. 6. Sequential Logic. SR-latch. Gated SR-latch. Gated D-latch. Flip-flops. Flip-flop types. Analysis of sequential logic. Finite-state-machine model. Synthesis of sequential logic. FSM model capture. State minimization. State encoding. Choice of memory elements. Optimization and timing. 7. Storage Components. Registers. Shift registers. Counters. BCD counter. Asynchronous counter. Register files. Random-access memories (RAMs). Push-down stacks. Firs- in-first-out queue. Simple datapaths. General datapaths. Control unit design. 8. Register-Transfer Design. Design model. FSMD definition. Algorithmic-state-machine charts. Synthesis from ASM charts. Register sharing (variable merging). Functional unit sharing (operator sharing). Bus sharing (connection merging). Register merging. Chaining and multicycling. Functional unit pipelining. ASM pipelining. Control- pipelining. Scheduling. 9. Processor Design. Instruction sets. Addressing modes. Processor design. Instruction set design. Processor design. Reduced instruction set. RISC Design. Data forwarding. Branch prediction.

Automatic synthesis of low-power gated-clock finite-state machines

Abstract: The automatic synthesis of low power finite-state machines (FSM's) with gated clocks relies on efficient algorithms for synthesis and optimization of dedicated clock-stopping circuitry. We describe a new transformation for incompletely specified Mealy-type machines that makes them suitable for gated-clock implementation with a limited increase in complexity. The transformation is probabilistic-driven, and identifies highly-probable idle conditions that will be exploited for the optimal synthesis of the logic block that controls the local clock of the FSM. We formulate and solve a new logic optimization problem, namely, the synthesis of a subfunction of a Boolean function that is minimal in size under a constraint on its probability to be true. We describe the relevance of this problem for the optimal synthesis of gated clocks. A prototype tool has been implemented and its performance, although influenced by the initial structure of the FSM, shows that sizable power reductions can be obtained using our technique.

Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions

Abstract: We present a new representation for Boolean functions called Partitioned ROBDDs. In this representation we divide the Boolean space into 'k' partitions and represent a function over each partition as a separate ROBDD. We show that partitioned-ROBDDs are canonical and can be efficiently manipulated. Further they can be exponentially more compact than monolithic ROBDDs and even free BDDs. Moreover, at any given time, only one partition needs to be manipulated which further increases the space efficiency. In addition to showing the utility of partitioned-ROBDDs on special classes of functions, we provide automatic techniques for their construction. We show that for large circuits our techniques are more efficient in space as well as time over monolithic ROBDDs. Using these techniques, some complex industrial circuits could be verified for the first time.

On the Fourier spectrum of monotone functions

Abstract: In this paper, monotone Boolean functions are studied using harmonic analysis on the cube. The main result is that any monotone Boolean function has most of its power spectrum on its Fourier coefficients of degree at most O(√n) under any product distribution. This is similar to a result of Linial et al. [1993], which showed that AC 0 functions have almost all of their power spectrum on the coefficients of degree, at most (log n) O(1) , under the uniform distribution. As a consequence of the main result, the following two corollaries are obtained : -For any e > 0, monotone Boolean functions are PAC learnable with error e under product distributions in time 2 O((1/e) √ n) . -Any monotone Boolean function can be approximated within error e under product distributions by a non-monotone Boolean circuit of size 2 O(1/e √ n) and depth O(1/e √n). The learning algorithm runs in time subexponential as long as the required error is Ω(1/(√n log n)). It is shown that this is tight in the sense that for any subexponential time algorithm there is a monotone Boolean function for which this algorithm cannot approximate with error better than O(1/√n). The main result is also applied to other problems in learning and complexity theory. In learning theory, several polynomial-time algorithms for learning some classes of monotone Boolean functions, such as Boolean functions with O(log 2 n/log log n) relevant variables, are presented. In complexity theory, some questions regarding monotone NP-complete problems are addressed.

Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams

Abstract: This paper proposes an efficient algorithm for technology mapping targeting table look-up (TLU) blocks. It is capable of minimizing either the number of TLUs used or the depth of the produced circuit. Our approach consists of two steps. First a network of super nodes, is created. Next a Boolean function of each super node with an appropriate don't care set is decomposed into a network of TLUs. To minimize the circuit's depth, several rules are applied on the critical portion of the mapped circuit.

A capacitive threshold-logic gate

Abstract: A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

Extracting Randomness: How and Why A survey

Abstract: Extractors are Boolean functions that allow, in some precise sense, extraction of randomness from somewhat random distributions. Extractors, and the closely related "Dispersers", exhibit some of the most "random-like" properties of explicitly constructed combinatorial structures. In turn, extractors and dispersers have many applications in "removing randomness" in various settings and in making randomized constructions explicit. This manuscript surveys extractors and dispersers: what they are, how they can be designed, and some of their applications. The work described is due to of a long list of research papers by various authors-most notably by David Zuckerman.

Genetic algorithm for variable ordering of OBDDs

Abstract: A genetic algorithm (GA) is applied to find a variable ordering that minimises the size of ordered binary decision diagrams (OBDDs). OBDDs are a data structure for representation and manipulation of Boolean functions often applied in CAD. The choice of the variable ordering largely influences the size of the OBDD (i.e. its size may vary from polynomial to exponential in the number of variables). Dynamic variable ordering is the state-of-the-art method for finding good variable orderings. In the paper it is shown by experimental results that better sizes can be obtained using GAs. The authors' GA approach is a practical alternative to the exact algorithm for variable ordering. It produced optimal results for most considered benchmarks, but it is also applicable to functions with more than 20 variables due to its short runtimes.

Theory of fault-based predicate testing for computer programs

Abstract: Predicates appear in both the specification and implementation of a program. One approach to software testing, referred to as predicate testing, is to require certain types of tests for a predicate. In this paper, three fault-based testing criteria are defined for compound predicates, which are predicates with one or more AND/OR operators. BOR (boolean operator) testing requires a set of tests to guarantee the detection of (single or multiple) boolean operator faults, including incorrect AND/OR operators and missing/extra NOT operators. BRO (boolean and relational operator) testing requires a set of tests to guarantee the detection of boolean operator faults and relational operator faults (i.e., incorrect relational operators). BRE (boolean and relational expression) testing requires a set of tests to guarantee the detection of boolean operator faults, relational operator faults, and a type of fault involving arithmetical expressions. It is shown that for a compound predicate with n, n>0, AND/OR operators, at most n+2 constraints are needed for BOR testing and at most 2*n+3 constraints for BRO or BRE testing, where each constraint specifies a restriction on the value of each boolean variable or relational expression in the predicate. Algorithms for generating a minimum set of constraints for BOR, BRO, and BRE testing of a compound predicate are given, and the feasibility problem for the generated constraints is discussed. For boolean expressions that contain multiple occurrences of some boolean variables, how to combine BOR testing with the meaningful impact strategy (Weyuker et al., 1994) is described.

Perturb and simplify: multilevel Boolean network optimizer

Abstract: In this paper, we present logic optimization techniques for multilevel combinational networks. Our techniques apply a sequence of perturbations which result in simplification of the circuit. The perturbation and simplification is achieved through wires/gates addition and removal which are guided by the Automatic Test Pattern Generation (ATPG) based reasoning. The main operations of our approaches are incremental transformations of the circuit (such as adding wires/gates and changing gate's functionality) to remove some particular wire, At each iteration, a summary information of such wires/gates addition and removal is precomputed first. Then, a transformation is chosen to remove several wires at once. We have performed experiments on MCNC benchmarks and compared the results to those of misII and RAMBO. Experimental results are very encouraging.

OBDD-based function decomposition: algorithms and implementation

Abstract: This paper presents algorithms for disjunctive and nondisjunctive decomposition of Boolean functions and Boolean methods for identifying common subfunctions from multiple Boolean functions. Ordered binary decision diagrams are used to represent and manipulate Boolean functions so that the proposed methods can be implemented concisely. These techniques are applied to the synthesis of look-up table based field programmable gate arrays and results are presented.

Fast OFDD-based minimization of fixed polarity Reed-Muller expressions

Abstract: We present methods to minimize fixed polarity Reed-Muller expressions (FPRMs), i.e., two-level fixed polarity AND/EXOR canonical representations of Boolean functions, using ordered functional decision diagrams (OFDDs). We investigate the close relation between both representations and use efficient algorithms on OFDDs for exact and heuristic minimization of FPRMs. In contrast to previously published methods, our algorithm can also handle circuits with several outputs. Experimental results on large benchmarks are given to show the efficiency of our approach.

Generalized Reed-Muller forms as a tool to detect symmetries

Abstract: In this paper, we present a new method for detecting groups of symmetric variables of completely specified Boolean functions. The canonical Generalized Reed-Muller (GRM) forms are used as a powerful analysis tool. To reduce the search space we have developed a set of signatures that allow us to identify quickly sets of potentially symmetric variables. Our approach allows for detecting symmetries of any number of inputs simultaneously. Totally symmetric functions can be detected very quickly. The traditional definitions of symmetry have also been extended to include more types. This extension has the advantage of grouping input variables into more classes. Experiments have been performed on MCNC benchmark cases and the results verify the efficiency of our method.

Representations of Logic Functions Using EXOR Operators

Abstract: Logic functions are usually represented by logical expressions or decision diagrams using AND and OR operators. However, some functions have more compact representations with EXOR operators. This chapter surveys representations of logic functions using EXOR operators.

Spectral Transform Decision Diagrams

Abstract: This chapter proposes spectral decision diagrams (STDDs), that are graphical representations of spectral transforms of switching functions and integer-valued functions. Binary decision diagrams (BDDs) and functional decision diagrams (FDDs) are graphical representations for switching functions and their Reed-Muller transforms, respectively. Multi-terminal decision diagrams (MTBDDs), arithmetic transform decision diagrams (ACDDs), and Walsh transform decision diagrams (WDDs) are graphical representations for integer-valued functions, their arithmetic transforms, and their Walsh transforms, respectively. This chapter shows that an STDD represents a function and its spectral transform at the same time. As for n-bit adders, ACDDs and WDDs require O(n) nodes while MTBDDs require O(2 n ) nodes. As for n-bit multipliers, ACDDs and WDDs require O(n 2) nodes while MTBDDs require O(4 n ) nodes.

An ordering heuristic for building binary decision diagrams from fault-trees

Abstract: Binary decision diagrams (BDD) have made a noticeable entry in the RAMS field. This kind of representation for Boolean functions makes possible the assessment of complex fault-trees, both qualitatively (minimal cutsets search) and quantitatively (exact calculation top event probability). Any Boolean function, and in particular any fault-tree, whether coherent or not, can be represented by a BDD. The BDD is a canonical representation of the function, as soon as one has chosen a variable (i.e., in the fault-tree case, basic event) ordering. Tools based on the use of BDDs, like METAPRIME, or ARALIA, can in some cases give more accurate results than conventional tools, while running 1000 times faster. EDF has investigated this kind of technology, and tested METAPRIME, ARALIA, and other tools based on BDDs, in the framework of cooperations with the BULL company and with the Bordeaux University. These tests have demonstrated that the size of the BDD, that has to be built thoroughly before any kind of assessment can begin, is dramatically sensitive to the ordering chosen for the variables. For a given fault-tree, this size may vary by several orders of magnitude. This can lead to excessive needs, both in terms of memory and CPU time. The problem of finding an optimal ordering being untractable for real applications, many heuristics have been proposed, in order to find acceptable orderings, at low cost (in terms of computing requirements).

On the correlation of symmetric functions

Abstract: Thecorrelation between two Boolean functions ofn inputs is defined as the number of times the functions agree minus the number of times they disagree, all divided by 2 n . In this paper we compute, in closed form, the correlation between any twosymmetric Boolean functions. As a consequence of our main result, we get that every symmetric Boolean function having an odd period has anexponentially small correlation (inn) with the parity function. This improves a result of Smolensky [12] restricted to symmetric Boolean functions: the correlation between parity and any circuit consisting of a Mod q gate over AND gates of small fan-in, whereq is odd and the function computed by the sum of the AND gates is symmetric, is bounded by 2−Ω(n).

Formal analysis of synchronous circuits

Abstract: This dissertation addresses three separate, but related problems concerning the formal analysis of synchronous circuits and their associated finite state machines. The first problem is the logical analysis of synchronous circuits containing combinational cycles. The presence of such cycles can cause unstable behavior at the outputs of a circuit, but this is not necessarily always the case. This work determines when cycles are harmless, and when they are not. In particular, three classes of circuits are defined that tradeoff time to decide the class, with the permissiveness of the class. For each class, the complexity of the corresponding decision problem is proven and a procedure to decide the class is given. In addition, if a circuit is determined to be within a given class, then a new circuit can be generated with the same input/output behavior, but without combinational cycles. This is an important utility, as many CAD tools do not accept circuits with combinational cycles. The second problem that is addressed is the CTL model checking of interacting FSMs. A state equivalence is presented that is defined with respect to a given CTL formula. Since it does not attempt to preserve all CTL formulas, like bisimulation does, we can expect to compute coarser equivalences. This equivalence is used to manage the size of the transition relations encountered when model checking a system of interacting FSMs. Specifically, the equivalence is used to reduce the size of each component FSM, so that their product will be smaller. We show how to apply the method, whether an explicit representation is used for the FSMs, or BDDs are used. Also, we show that in some cases this approach can detect if a formula passes or fails, without composing all the component machines. The method is exact and completely automatic, and handles full CTL. These two problems are PSPACE-hard (in the number of flip-flops) to decide; approximate methods may be useful to find a solution in affordable CPU time. To demonstrate the use of approximate methods in logical analysis, we address the the state reachability problem in FSMs, which is the problem of determining if one set of states can reach another. State reachability has broad applications in formal verification, synthesis, and testing of synchronous circuits. This work attacks this problem by making a series of under- and over-approximations to the state transition graph, using the over-approximations to guide the search in the under-approximations for a potential path from one state set to the other. Central to this method is an algorithm to approximate a Boolean function by another function having a smaller BDD.

A satisfiability-based test generator for path delay faults in combinational circuits

Abstract: The paper describes a new formulation to generate robust tests for path delay faults in combinational circuits based on Boolean satisfiability. Conditions to detect a target path delay fault are represented by a Boolean formula. Unlike the technique described by A. Saldhana et al. (1992), which extracts the formula for each path delay fault, the proposed formulation needs to extract the formula only once for each circuit cone. Experimental results show tremendous time saving on formula extraction compared to other satisfiability based ATPG algorithms. This also leads to low test generation time, especially for circuits that have many paths but few outputs. The proposed formulation has also been modified to generate other types of tests for path delay faults.

Power-Law Distributions in Some Random Boolean Networks.

Abstract: The Kauffman net is a dynamical system of logical variables receiving two random inputs and each randomly assigned a Boolean function. We show that the attractor and transient lengths exhibit scaleless behavior with power-law distributions over up to 10 orders of magnitude in probability. Our results provide evidence for the existence of the ``edge of chaos'' as a distinct regime between the ordered and chaotic phases analogous to a critical point in statistical mechanics. The power-law distributions are robust to the changes in the composition of the transition rules and network dynamics.

Combining ambiguous evidence with respect to ambiguous a priori knowledge. I. Boolean logic

Abstract: This paper describes conditioned Dempster-Shafer (CDS) theory, a probabilistic calculus for dealing with possibly non-Bayesian evidence when the underlying a priori knowledge base is possibly non-Bayesian. Specifically, we show that the Dempster-Shafer combination operator can be "conditioned" to reflect the influence of any a priori knowledge base which can be modeled by a Dempster-Shafer belief measure. We show that CDS is firmly grounded in probability theory-specifically, in the theory of random sets. We also show that it is a generalization of the Bayesian theory to the case when both evidence and a priori knowledge are ambiguous. We derive the algebraic properties of the theory when a priori knowledge is assumed fixed. Under this assumption, we also derive the form of CDS in the special case when fixed a priori knowledge is Bayesian.

Using BDDs to Design ULMs for FPGAs

Abstract: Many modern FPGAs use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. Since permutations and negation of signals are virtually costless operations in FPGAs, it is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have only recently been considered for application in FPGAs. In this paper we propose a class of ULMs useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on BDD description of logic functions. We give an explicit construction of a 3-input LUT replacement that requires only 5 programming bits, which is the optimum for such ULMs. A realistic size 4-input LUT replacement is obtained which uses 13 programming bits. Such logic blocks are especially important when FPGAs are used in a reconfigurable manner, because they can reduce the time and memory needed for changing the configuration.

MORE: an alternative implementation of BDD packages by multi-operand synthesis

Abstract: In this paper we present a new approach for the realization of a BDD package. This approach does not depend on recursive synthesis operations, i.e. the ternary If-Then-Else-operator (ITE), to perform manipulations of Boolean functions; instead our basic operation MORE is based on exchanges of neighbouring variables and existential quantification. It is capable of combining an arbitrary number of Boolean functions in parallel. We discuss the difference between MORE and ITE and give experimental results to show the advantages of our implementation approach with respect to size and runtime.

A training framework for stack and Boolean filtering-fast optimal design procedures and robustness case study

Abstract: A training framework is developed in this paper to design optimal nonlinear filters for various signal and image processing tasks. The targeted families of nonlinear filters are the Boolean filters and stack filters. The main merit of this framework at the implementation level is perhaps the absence of constraining models, making it nearly universal in terms of application areas. We develop fast procedures to design optimal or close to optimal filters, based on some representative training set. Furthermore, the training framework shows explicitly the essential part of the initial specification and how it affects the resulting optimal solution. Symmetry constraints are imposed on the data and, consequently, on the resulting optimal solutions for improved performance and ease of implementation. The case study is dedicated to natural images. The properties of optimal Boolean and stack filters, when the desired signal in the training set is the image of a natural scene, are analyzed. Specifically, the effect of changing the desired signal (using various natural images) and the characteristics of the noise (the probability distribution function, the mean, and the variance) is analyzed. Elaborate experimental conditions were selected to investigate the robustness of the optimal solutions using a sensitivity measure computed on data sets. A remarkably low sensitivity and, consequently, a good generalization power of Boolean and stack filters are revealed. Boolean-based filters are thus shown to be not only suitable for image restoration but also robust, making it possible to build libraries of "optimal" filters, which are suitable for a set of applications.

Formal verification using edge-valued binary decision diagrams

Abstract: We present a new data structure called edge-valued binary-decision diagrams (EVBDD). An EVBDD is a directed acyclic graph, that provides a canonical and compact representation of functions that involve both Boolean and integer quantities. In general, EVBDDs provide a more versatile and powerful representation than ordinary binary decision diagrams. We first describe the structure and properties of EVBDDs, and present a general algorithm for performing a variety of binary operations. Next, we describe an important extension of EVBDDs, called Structural EVBDDs, and show how they can be used for hierarchical verification.