Showing papers on "Chip published in 2016"

A Highly Integrated 60 GHz 6-Channel Transceiver With Antenna in Package for Smart Sensing and Short-Range Communications

Abstract: This work presents a highly integrated 57–64 GHz 4-channel receiver 2-channel transmitter chip targeting short range sensing and large bandwidth communications. The chip is housed in an embedded wafer level ball grid array package. The package includes 6 integrated patch antennas realized with a metal redistribution layer. The receiver patch antennas have a combined antenna gain of $\approx 10$ dBi while each transmitter antenna has a gain of $\approx ~6$ dBi. The chip features a wide tuning range integrated VCO with a measured phase noise lower than −80 dBc/Hz at 100 kHz offset. Each of the differential transmitter channels shows a measured output power of 2–5 dBm over the complete frequency range. In addition, one transmitter channel features a modulator that can be digitally programmed to operate in either radar or communication mode. Each of the receiver channels has a measured conversion gain of 19 dB, a single-sideband noise figure of less than 10 dB and an input referred 1 dB compression point of less than 10 dBm. With all channels turned on the chip consumes a current of 300 mA from a 3.3 V supply. The functionality of the chip is demonstrated for both sensing and short range wireless communications.

Demonstration of a chip-based optical isolator with parametric amplification.

Abstract: Despite being fundamentally challenging in integrated (nano)photonics, achieving chip-based light non-reciprocity becomes increasingly urgent in signal processing and optical communications. Because of material incompatibilities in conventional approaches based on the Faraday effect, alternative solutions have resorted to nonlinear processes to obtain one-way transmission. However, dynamic reciprocity in a recent theoretical analysis has pinned down the functionalities of these nonlinear isolators. To bypass such dynamic reciprocity, we here demonstrate an optical isolator on a silicon chip enforced by phase-matched parametric amplification in four-wave mixing. Using a high-Q microtoroid resonator, we realize highly non-reciprocal transport at the 1,550 nm wavelength when waves are injected from both directions in two different operating configurations. Our design, compatible with current complementary metal-oxide-semiconductor (CMOS) techniques, yields convincing isolation performance with sufficiently low insertion loss for a wide range of input power levels. Moreover, our work demonstrates the possibility of designing chip-based magnetic-free optical isolators for information processing and laser protection. Non-reciprocal optical elements usually require the presence of magnetic fields, which makes chip integration difficult. Here, Hua et al. demonstrate a non-magnetic optical isolator with bidirectional injection on a silicon platform utilizing parametric amplification in four-wave mixing.

Wireless charging with multiple power receiving facilities on a wireless device

Abstract: The disclosed system utilizes multiple wireless power receivers (antennas and or paths) for receiving power. The disclosed system includes a chip, such as an application specific chip (ASICs) connectable to multiple antennas and units to convert radio frequency (RF) power into direct current (DC) power. The disclosed system can also include antennas that are used to receiving power, communicate, and send a beacon signal. The disclosed system also comprises a mobile electronic device to receive wireless power using multiple antennas connected or coupled to multiple wireless power receivers.

Wide-range, high-precision multiple microwave frequency measurement using a chip-based photonic Brillouin filter

Abstract: Spectrum analysis is a key functionality in modern radio frequency (RF) systems. In particular, fast and accurate estimation of multiple unknown RF signal frequencies over a wide measurement range is crucial in defense applications. Although photonic techniques benefit from an enhanced frequency estimation range along with reduced size and weight relative to their RF counterparts, they have been limited by a fundamental trade-off between measurement range and accuracy. Here, we circumvent this trade-off by harnessing the photon and phonon interactions in a photonic chip through stimulated Brillouin scattering, resulting in an accurate estimation of multiple RFs of up to 38 GHz with a record-low error of 1 MHz.

Optical coherence tomography system mass-producible on a silicon photonic chip.

Abstract: Miniaturized integrated optical coherence tomography (OCT) systems have the potential to unlock a wide range of both medical and industrial applications. This applies in particular to multi-channel OCT schemes, where scalability and low cost per channel are important, to endoscopic implementations with stringent size demands, and to mechanically robust units for industrial applications. We demonstrate that fully integrated OCT systems can be realized using the state-of-the-art silicon photonic device portfolio. We present two different implementations integrated on a silicon-on-insulator (SOI) photonic chip, one with an integrated reference path (OCTint) for imaging objects in distances of 5 mm to 10 mm from the chip edge, and another one with an external reference path (OCText) for use with conventional scan heads. Both OCT systems use integrated photodiodes and an external swept-frequency source. In our proof-of-concept experiments, we achieve a sensitivity of −64 dB (−53 dB for OCTint) and a dynamic range of 60 dB (53 dB for OCTint). The viability of the concept is demonstrated by imaging of biological and technical objects.

High Level Synthesis Introduction To Chip And System Design

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An Eight-Element 2–16-GHz Programmable Phased Array Receiver With One, Two, or Four Simultaneous Beams in SiGe BiCMOS

Abstract: This paper presents an eight-element 2–16-GHz programmable phased array (PPA) receiver in a 0.13- $\mu \text{m}$ SiGe BiCMOS with the reconfigurable number of beams and with the digital beamforming (DBF) capabilities. The eight-element chip can be configured for one, two, or four simultaneous beams or as an element-level DBF receiver. This is achieved using reconfigurable input switching and output combining networks with wideband active switches and combiners. The phased array channel results in a 5-b performance at 3–14 GHz (rms error $P_{\text {1 dB}}$ of −20 dBm per channel when all channels are activated. The chip consumes 250 mW per channel, which is competitive knowing its bandwidth and linearity. The DBF function also results in a wideband response with a gain and an NF of 15–16 and 12–13 dB, respectively, and high linearity (input $P_{\text {1 dB}} = -16$ dBm) at 2–16 GHz. The programmable phased array receiver allows a single chip to be used over $S$ -, $C$ -, $X$ -, and $Ku$ -bands for a variety of applications such as satellite communications and point-to-point links. This results in faster and lower-cost phased array development since the same chip and its field-programmable gate array control can be reused from system to system, but with different antenna and grid spacing. The PPA removes the need to develop a different chip for every application and allows the development of phased arrays at commercial scales.

Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication

Abstract: Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Integrated optical switch matrices for packet data networks

Abstract: Integrated circuit technologies are enabling intelligent, chip-based, optical packet switch matrices. Rapid real-time re-configurability at the photonic layer using integrated circuit technologies is expected to enable cost-effective, energy-efficient, and transparent data communications. InP integrated photonic circuits offer high-performance amplifiers, switches, modulators, detectors, and de/multiplexers in the same wafer-scale processes. The complexity of these circuits has been transformed as the process technologies have matured, enabling component counts to increase to many hundreds per chip. Active–passive monolithic integration has enabled switching matrices with up to 480 components, connecting 16 inputs to 16 outputs. Integrated switching matrices route data streams of hundreds of gigabits per second. Multi-path and packet time-scale switching have been demonstrated in the laboratory to route between multiple fibre connections. Wavelength-granularity routing and monitoring is realised inside the chip. In this paper, we review the current status in InP integrated photonics for optical switch matrices, paying particular attention to the additional on-chip functions that become feasible with active component integration. We highlight the opportunities for introducing intelligence at the physical layer and explore the requirements and opportunities for cost-effective, scalable switching. Devices that can quickly redirect incoming packets of optically encoded data could substantially increase the speed of the Internet. Kevin Williams and colleagues have reviewed recent developments in large optical switch matrices with a particular focus on the work performed using Indium phosphide integrated photonics at the Eindhoven University of Technology in the Netherlands. Indium phosphide is a semiconducting material that can efficiently produce and amplify light. Optically active switches made from a single material can improve operation speed and reduce the optical and electrical energy consumption of the device. Thus, indium phosphide integrated photonic circuits can combine advanced routing and signal processing functions all on one chip. So far this technology has created switching matrices with up to 480 components, connecting sixteen inputs to sixteen outputs and routed data streams at rates of a few hundred Gigabits per second.

Multichannel 65 zF rms Resolution CMOS Monolithic Capacitive Sensor for Counting Single Micrometer-Sized Airborne Particles on Chip

Abstract: The first integrated CMOS monolithic sensor system for on-chip capacitive detection of micrometric airborne particulate matter (PM) is presented. The chip is based on a 32 channel lock-in architecture allowing a dust collection area of 1.15 mm2 where interdigitated differential microelectrodes, fabricated with the top metal and directly exposed to air, allow single particle sensitivity. The preamplifier input capacitance is significantly minimized thanks to the electrode–amplifier proximity and proper partitioning of the sensing area, in order to reduce the noise. Each channel comprises a charge preamplifier with adjustable high-pass filtering for flicker noise shaping, square-wave mixer, $g_{m}$ -C tunable low-pass filter (40–750 Hz), and a 6 bit digital network for automatic compensation of electrodes mismatching with a granularity of 150 aF. Thanks to the capacitive noise of only 65 zF rms with 25 ms temporal resolution, deposition events of single mineral talc particles were recorded down to 1 $\mu \text{m}$ diameter with a signal-to-noise ratio of $\approx 18$ dB. This chip paves the way to pervasive mapping of both indoor and outdoor PM in the 1–30 $\mu \text{m}$ range.

Experimental verification of on-chip CMOS fractional-order capacitor emulators

Abstract: The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS.

Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields

Abstract: For a quantum computer, switching a signal carried by single microwave photons is desirable in scaling up superconducting circuitry. The authors design and build such a switch, integrate it on a chip with a single-photon source, and prove that it works with nonclassical microwave input. Their device offers negligible heating, relatively large bandwidth, low nonlinearity, and single-pole double-throw switching in mere nanoseconds. It is well suited for applications where signal routing must be controlled by real-time feedback, as in multiplexing qubit control and readout, or distributing entanglement in quantum networks.

Dynamic security codes, tokens, displays, cards, devices, multi-card devices, systems and methods

Abstract: A dynamic code of a transaction device may be validated by a remote processor by comparing the dynamic code to a verification code generated using a timestamp and identification data received from the transaction device. A static code may replace the dynamic code for authorization processing. A remote verification processor may synchronize to the transaction device using the timestamp. A token may be associated to each communication interface of a multi-card transaction device. A display may be directly connected to driver circuit on a display board of a transaction card. A radio IC chip may be included in a powered card. A multi-card device may toggle a plurality of display screens to display transaction data.

Over 10 a operation with switching characteristics of 1.2 kV-class vertical GaN trench MOSFETs on a bulk GaN substrate

Abstract: In this paper, we demonstrate 1.2 kV-class vertical GaN trench MOSFETs fabricated on a bulk GaN substrate with high current and switching operations. The fabricated multi-cell MOSFET achieved a blocking voltage of 1.3 kV by using a field-plate edge termination around an isolation mesa. The MOSFET chip with the size of 1.5 mm × 1.5 mm operates at current rating of as high as 23.2 A with fast switching characteristics. To our knowledge, this is the first report for vertical GaN-based transistors with a high current operation exceeding 10 A and dynamic characteristics.

An all-glass 12 μm ultra-thin and flexible micro-fluidic chip fabricated by femtosecond laser processing.

Abstract: This study investigated and established a method, using femtosecond laser processing, to fabricate a 100%-glass-based 12 μm ultra-thin and flexible micro-fluidic chip. First we investigated the suitable pulse energy of the laser to fabricate ultra-thin glass sheets and then we fabricated a prototype glass micro-fluidic chip. Two 1 mm-in-diameter orifices for facilitating alignment in the bonding step and one channel with a width of 20 μm and a length of 25 mm were fabricated in a 4 μm thickness ultra-thin glass sheet using the femtosecond laser; this forms layer 2 in the completed device. Next, the glass sheet with the channel was sandwiched between another glass sheet having an inlet hole and an outlet hole (layer 1) and a base glass sheet (layer 3); the three sheets were bonded to each other, resulting in a flexible, 100%-glass micro-fluidic chip with a thickness of approximately 12 μm and a weight of 3.6 mg. The basic function of the glass micro-fluidic chip was confirmed by flowing 1 and 2 μm in-diameter bead particles through the channel. The fabrication method clearly scales down the thickness limitation of flexible glass devices and offers a possible element technology for fabricating ultra-thin glass devices that can be applied to convection-enhanced delivery, implantable medical devices, wearable devices, and high-resolution imaging of small biological objects such as bacteria and proteins in the channel.

Random design of microfluidics

Abstract: In this work we created functional microfluidic chips without actually designing them. We accomplished this by first generating a library of thousands of different random microfluidic chip designs, then simulating the behavior of each design on a computer using automated finite element analysis. The simulation results were then saved to a database which a user can query via to find chip designs suitable for a specific task. To demonstrate this functionality, we used our library to select chip designs that generate any three desired concentrations of a solute. We also fabricated and tested 16 chips from the library, confirmed that they function as predicted, and used these chips to perform a cell growth rate assay. This is one of many different applications for randomly-designed microfluidics; in principle, any microfluidic chip that can be simulated could be designed automatically using our method. Using this approach, individuals with no training in microfluidics can obtain custom chip designs for their own unique needs in just a few seconds.

Orthogonal Power Division Multiple Access: A Green Communication Perspective

Abstract: In cellular networks, since Media Access Control (MAC) layer plays a key role in every access equipment, it fascinates that little progress on multiple access protocol could save considerable energy. Accordingly, this paper studies a novel MAC protocol, i.e., the power division multiple access (PDMA) protocol, with the purpose of green communication. As a fundamental study of PDMA, we first propose a power division multiplexing (PDM) scheme, analogous to the time division multiplexing and frequency division multiplexing. It is proved that the transmit power could be divided into multiple regular power segments (PSs) to simultaneously transmit multiple independent information/data streams in peer to peer communications. Based on our fundamental studies of PDM, an orthogonal PDMA (OPDMA) protocol is proposed to utilize multiplexing and degraded channel gains for energy saving. By adopting the orthogonal PSs proposed in OPDMA, multiple information streams in different channels could be transmitted efficiently and concurrently with quality of service guarantee. This paper shows that the proposed OPDMA not only has low computational complexity as the conventional Time Division Multiple Access (TDMA) and Frequency Division Multiple Access (FDMA) protocols but also gains better energy efficiency, which consists with the energy saving requirement in green communications.

Harmonic Power Harvesting System for Passive RFID Sensor Tags

Abstract: This paper introduces a relevant concept of energy harvesting for passive UHF radio frequency identification (RFID) relying on the exploitation of the power carried by the third harmonic signal generated by the RFID chip. The idea consists on the use of the sole third harmonic energy to power up an associated sensor to the RFID tag. The proposed concept is first demonstrated in simulation thanks to an equivalent model for the RF front-end of a passive UHF RFID chip. Although the proposed model is simplified, it considers the generated nonlinear signals, allowing an efficient design of the rectifier circuit, which is responsible of harvesting the third harmonic power besides ensuring the activation of the RFID chip in order to communicate with the reader. The power driving between the RFID chip, third harmonic harvester, and antenna at the fundamental and third harmonic frequencies is achieved by designing a low-loss distributed three-port impedance matching network. Simulation results confirm the operation of the matching network and the exploitation of the third harmonic signal by analyzing the power at different nodes in the circuit. Measurement results validate the proposed nonlinear chip model. A prototype of the RFID tag harmonic-harvester produces 39 $\mu \text{W}$ of dc power harvested from the harmonic signal, showing good agreement with the simulation results. Finally, a sensor application exploiting the harmonic harvested power to energize a commercial temperature sensor at a distance of 80 cm from the reader is demonstrated.

WDM-Enabled Optical RAM at 5 Gb/s Using a Monolithic InP Flip-Flop Chip

Abstract: We experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6×2 mm 2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance.

Increasing Electrochemiluminescence Intensity of a Wireless Electrode Array Chip by Thousands of Times Using a Diode for Sensitive Visual Detection by a Digital Camera.

Abstract: Both a wireless electrochemiluminescence (ECL) electrode microarray chip and the dramatic increase in ECL by embedding a diode in an electromagnetic receiver coil have been first reported. The newly designed device consists of a chip and a transmitter. The chip has an electromagnetic receiver coil, a mini-diode, and a gold electrode array. The mini-diode can rectify alternating current into direct current and thus enhance ECL intensities by 18 thousand times, enabling a sensitive visual detection using common cameras or smart phones as low cost detectors. The detection limit of hydrogen peroxide using a digital camera is comparable to that using photomultiplier tube (PMT)-based detectors. Coupled with a PMT-based detector, the device can detect luminol with higher sensitivity with linear ranges from 10 nM to 1 mM. Because of the advantages including high sensitivity, high throughput, low cost, high portability, and simplicity, it is promising in point of care testing, drug screening, and high throughput a...

Circuits for efficient detection of vector signaling codes for chip-to-chip communication

Abstract: In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Low-loss and Broadband G-Band Dielectric Interconnect for Chip-to-Chip Communication

Abstract: This paper presents a novel dielectric waveguide based G-band interconnect. By using a new transition of microstrip line to dielectric waveguide, the interconnect achieves low insertion loss and wide bandwidth. The measured minimum insertion loss is 4.9 dB with 9.7 GHz 1-dB bandwidth. Besides, the structure is based on standard micromachined processing and easy to integrate with conventional packaging.

Semiconductor device, solid-state image sensor and camera system

Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.

6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers

Abstract: Recently, there has been strong demand for high-resolution CMOS image sensors (large number of pixels) in the fields of security, science, and other specialized areas [1,2]. One of the major issues in realizing high-resolution image sensors is to speed up signal readout. For high-speed signal readout, it is necessary to accelerate pixel readout, AD conversion in column circuits, horizontal data output from column memories, and digital data output from the chip. Single-slope ADCs (SS-ADC) are the most common architecture in commercialized CMOS image sensors; increasing their counting clock frequency up to 2.376GHz [3] and using multiple ramp signals [4] can shorten the AD conversion period. However, the former has difficulty in maintaining the clock quality and suppressing power dissipation due to the high clock frequency, and the latter has difficulty in controlling the uniformity and the quality of the multiple ramp signals. Another significant issue is power consumption. Rise of power consumption with increase in number of columns results in non-uniformity of power supply to the column circuits due to IR drops. It may give rise to degradation of image quality such as fixed pattern noise, etc.

Integrated Space-Division Multiplexer for Application to Data Center Networks

Abstract: The prospect of creating integrated space-division multiplexing (SDM) on a chip, utilizing the orthogonal degrees of freedom of numerous guided spatial modes in a multimode waveguide, promises a substantial reduction in the cost, complexity, and scalability of networking systems by augmenting or replacing the commonly used approach of wavelength-division multiplexing (WDM). As a demonstration of the SDM approach, we introduce and experimentally characterize a periodically nanostructured resonant coupler integrated with a multimode waveguide that selectively transfers energy between arbitrary waveguide modes. Compared to alternative schemes, this device possesses advantages in terms of packing density, control of operating bandwidth, tunability to operate with numerous orthogonal spatial modes, and support of a large number of switching ports.

A 500-MHz, 0.76-W/mm Power Density and 76.2% Power Efficiency, Fully Integrated Digital Buck Converter in 65-nm CMOS

Abstract: In this paper, we propose a 500-MHz on -chip digitally controlled buck converter in which active and passive components are fully integrated on a single CMOS chip. To achieve high-power density, a two-phase interleaving buck converter with negatively coupled inductors is adopted to reduce the silicon area for both inductors and output capacitors. In addition, the proposed on -chip stacked L/C structure can achieve 20% area-saving. Furthermore, to support a 500-Hz switching frequency, we present a low-power digital pulsewidth modulation (PWM) controller that includes a 9-bit time-based analog-to-digital converter and a 15%–90% wide-range digital pulsewidth modulator (DPWM), which occupies only $0.075 \text{ mm}^{2}$ and dissipation of 3 mW. The prototype IC fabricated in 65-nm CMOS can convert a 2.2-V input to a 1.2-V output and achieve a peak power efficiency of 76.2% and maximum power density of $0.76\ {\rm W/mm}^{2}$ . Simultaneously, it can deliver 0.84 W and occupy $1.1 \text{ mm}^{2}$ of effective area that includes a pair of 1.54-nH on -chip inductors and 2.63-nF on -chip capacitors.