Showing papers on "Digital electronics published in 1990"

The limitations to delay-insensitivity in asynchronous circuits

Abstract: Asynchronous techniques —that is, techniques that do not use clocks to implement sequencing— are currently attracting considerable interest for digital VLSI circuit design, in particular when the circuits produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive.

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

Abstract: The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >

Logic synthesis for programmable gate arrays

Abstract: The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures. >

Gate sizing in MOS digital circuits with linear programming

Abstract: In this paper a solution is presented to tune the delay of a circuit composed of cells to a prescribed value, while minimizing power consumption. The tuning is performed by adapting the load drive capabilities of the cells. This optimization problem is mapped onto a linear program, which is then solved by the Simplex algorithm. This approach guarantees to find the global optimum, and has proven feasible for circuits of up to several thousand cells. The method can be used with any convex delay model. Results show that circuits can be speeded up by a factor of 2 at a cost of only 10 to 30% of extra power.

Performance-oriented technology mapping

Abstract: This thesis presents a variety of techniques to minimize circuit delay during the translation of a set of Boolean equations into a list of connected logic gates that can be used for the manufacturing of combinational digital circuits. This translation process is called technology mapping. The first contribution of this work is to present an optimal algorithm to implement a Boolean circuits that can be represented as trees using an extension of known tree covering algorithms. The second and more important contribution of this work is an in-depth analysis of fanout optimization. The fanout problem is the problem of distributing a signal to several destinations, where the signal may be required at different times, in order to minimize the overall delay. This work presents the most detailed theoretical study of the complexity of fanout optimization published so far, and a spectrum of heuristics to solve the fanout problem under realistic delay models. This thesis also introduces a simple algorithm that can be used to apply fanout optimization to an entire network. This algorithm yields an optimal application of fanout optimization in terms of delay, while keeping area increase of the circuit to a low value. To study the integration of tree covering and fanout optimization, this work introduces a technology independent delay model that characterizes precisely suboptimalities due to inbalances in a network. This is the first technology independent delay model that models the delay through a node as a function of the arrival time distribution at a node. This delay model can be used to derive analytically optimal solutions in simple cases, which can be used to measure the suboptimality of heuristics. An extension to tree covering is then suggested, and shown to provide significant delay reductions for a relatively heavy cost in area. Finally this work investigates technology independent delay optimization techniques based on partial or total collapsing of logic, and shows that further delay reductions can be achieved with these techniques possibly at a higher cost in area.

Synchronization in digital system design

Abstract: A unified framework and terminology is presented for synchronization design in digital systems, borrowing techniques and terminologies from digital system and digital communication design disciplines. The throughput of synchronous and asynchronous interconnect is compared, emphasizing how it is affected by interconnect delay. A discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay. >

Secure random number generation using chaotic circuits

Abstract: The authors suggest a class of circuits for generating secure pseudo-random numbers and estimate the security of these generators from the information loss property of chaotic systems. For a generator implemented using a chaotic DPLL (digital phase-locked loop), two important cases are considered: (1) given no prior information concerning the initial conditions of a continuously running circuit, the length of time one should wait after taking a bit before one can securely take another bit is established; and (2) given knowledge of the initial conditions at startup (up to measurement and noise uncertainty), the length of time one should wait before starting the bit sampling is shown. >

CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits

Abstract: Two CAD tools, checkT/sub c/ and minT/sub c/, for timing verification and optimal clocking are introduced. Both tools are based on a new timing model of synchronous digital circuits. The model has the following features: (1) it is general enough to handle arbitrary multiphase clocking; (2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; (3) extensible to make it relatively easy to incorporate 'complex' latching structures; and (4) notationally simple to make it amenable to analytic treatment in some important special cases. These tools are being used to help in the design of a 4 ns gallium arsenide micro-supercomputer. >

A unified single-phase clocking scheme for VLSI systems

Abstract: Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme is general, simple, and safe. It provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs. Clock and data signals are presented in a clean way that makes VLSI circuits and systems well suited for design compilation. >

Foundations of electrical engineering

Abstract: I. CIRCUITS. 1. Basic Circuit Theory. 2. The Analysis of DC Circuits. 3. The Dynamics of Circuits. 4. The Analysis of AC Circuits. 5. Power in AC Circuits. 6. Electric Power Systems. II. ELECTRONICS. 7. Semiconductor Devices and Circuits. 8. Digital Electronics. 9. Analog Electronics. III. SYSTEMS 10. Instrumentation Systems. 11. Communication Systems. 12. Linear Systems. IV. MOTORS. 13. The Physical Basis of Electromagnetics. 14. Magnetic Structures and Electrical Transformers. 15. The Synchronous Machine. 16. Induction Motors. 17. Direct-Current Motors. 18. Power Electronic Systems. Index.

Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons

Abstract: A wafer-scale-integration (WSI) neural network has been fabricated and evaluated. 576 digital neurons are integrated and interconnected with each other on a 5-in silicon wafer by using 0.8-mm CMOS. Neural functions are faithfully mapped to binary digital circuits. The 9-bit output and the 8-bit synapse weight of each neuron are variable. A time-sharing digital bus architecture overcomes the disadvantage of digital neuron circuits. This WSI neural network can be connected with a host computer and used for a wide range of artificial neural networks. The 16-city traveling salesman problem could be solved in less than 0.1 s by using this network. This speed was 10 times faster than a Hitachi supercomputer. Larger artificial neural networks can be realized by simply connecting WSIs

A finite-difference transmission line matrix method incorporating a nonlinear device model

Abstract: A variable-mesh combination of the expanded-node transmission line matrix (TLM) and finite-difference-time-domain (FD-TD) methods for solving time-domain electromagnetic problems is described. It retains the physical process of wave propagation and the numerical stability of the former and it has the computational efficiency of the latter. This full-wave finite-difference transmission line matrix (FD-TLM) method utilizes transmission lines of differing impedances to implement a three-dimensional variable mesh, which makes practical the simulation of structures having fine details, such as digital integrated circuits (ICs). Circuit models for lumped resistors, capacitors, diodes, and MESFETs have been developed and included for use in simulating digital and microwave ICs. The validity of the variable mesh implementation is verified by comparing an FD-TLM simulation of a picosecond pulse generator structure with electrooptical measurements, and the validity of the device model implementation is verified by comparing an FD-TLM simulation of a MESFET logic inverter with a SPICE simulation. >

Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

Abstract: Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits. >

Formal Verification of Digital Circuits Using Symbolic Ternary System Models

Abstract: Ternary system modeling involves extending the traditional set of binary values {0, 1} with a third value X indicating an unknown or indeterminate condition. By making this extension, we can model a wider range of circuit phenomena. We can also efficiently verify sequential circuits in which the effect of a given operation depends on only a subset of the total system state.

CMOS source-coupled logic for mixed-mode VLSI

Abstract: A fully differential source-coupled logic technique intended for mixed-mode applications has been developed. Implemented in 2- mu m CMOS technology with a 5.0-V supply, the minimum propagation delay is about 750 ps with an 800-mV logic swing. Power supply current spikes are reduced by about two orders of magnitude compared to conventional static CMOS logic. >

Don't care minimization of multi-level sequential logic networks

Abstract: The authors address the problem of computing sequential don't cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to their approach is the use of binary decision diagram (BDD)-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described, exact sequential don't care sets for circuits with over 10/sup 68/ states have been successfully computed. >

Analysis and design of latch-controlled synchronous digital circuits

Abstract: A new formulation of the timing constraintss for latch-controlled synchronous digital circuits is presented. The authors show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. An LP-based algorithm is presented which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. An initial implementation of this LP-based solution procedure is illustrated for two example circuits. >

Quiescent current sensor circuits in digital VLSI CMOS testing

Abstract: Many integrated circuit processing defects may cause changes in the value of the quiescent power supply current. Not all of these changes are detectable using classical functional testing techniques. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide set of well known physical defects (including bridges and stuck-on). Two quiescent current sensor circuits are proposed and discussed. These circuits are oriented to different testing applications such as the external functional ATE environment, and the built-in self-testing (BIST) design for both on-line and off-line strategies. >

Efficient automatic diagnosis of digital circuits

Abstract: The problem of automatic diagnosis of digital circuits with efficiency is studied. Two improvements over the method of J.C. Madre et al. (1989) are developed to enhance the efficiency of diagnosis. Specifically, the dominance relation in circuit topology is utilized to reduce the search space of possibly correctable gates. In the authors' experiment, the search space is reduced to about one-half. A novel divide-and-conquer technique to determine the correct gate function is proposed. >

An algorithm for locating logic design errors

Abstract: Discusses the problem of locating logic design errors, and proposes an algorithm to solve it. Based on the results of logic verification, the authors introduce an input pattern for locating design errors. The pattern contains only one Boolean variable X/X and is used to sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors. >

Toward massively parallel automatic test generation

Abstract: A new automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. This approach is radically different from the conventional methods used to generate tests for circuits from their gate level description. The digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. The authors simulated the neural network on a serial computer, and determined the global minima of the energy function using a directed search technique augmented by probabilistic relaxation. Preliminary results on combinational circuits confirm the feasibility of this technique. >

Simulation techniques for mixed analog/digital circuits

Abstract: The techniques used in the iSPLICE3 simulator for the analysis of mixed analog/digital circuits are described. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes and uses event driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The contributions here include a new DC solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided, along with the architecture and transient simulation algorithms used in iSPLICE3. The results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy. >

A novel CMOS implementation of double-edge-triggered flip-flops

Abstract: A CMOS implementation of a D-type double-edge-triggered flip-flop (DET-FF) is presented. A DET-FF changes its state at both the positive and the negative clock edge transitions. It has advantages with respect to both system speed and power dissipation. The design presented requires little overhead in circuit complexity. This CMOS D-type DET-FF is capable of operating at more than 50 MHz, which gives an equivalent system frequency of 100 MHz. >

Method and apparatus to improve static path analysis of digital circuits

Abstract: The method of the present invention includes steps wherein a circuit designer, using standard computer assisted design (CAD) tools, designs a circuit which may include multi-cycle paths (MCPs). The designer inserts a conceptual circuit element, referred to as a "path breaker" into multi-cycle paths, such that the result is to convert all multi-cycle paths into single cycle paths. The designer then utilizes functional simulation software to edit the circuit design. To the simulator, a path breaker appears to be a latch in which the latch output goes to an unknown state when the input changes, and remains so until the output has been clocked and is equal to the input. Traditional logic synthesis is then performed on the circuit such that a net list is generated which includes the path breakers. Based on the net list, a post processor determines where in the circuit multi-cycle paths exist and generates a net list without path breakers, as well as a list of the multi-cycle paths. The list of multi-cycle paths is provided to a static path analysis program where the locations of the multi-cycle paths denote exceptions. Timing analysis is then performed, and if the circuit is satisfactory, fabrication may be completed using the net list without the conceptual path breakers.

Analog components for the VLSI of neural networks

Abstract: Principles of operation and basic building blocks of artificial neural networks are described. Deterministic components, comprising variable linear conductance devices and components used for processing elements, are discussed. These devices are analyzed using SPICE. The reasons for using simple analog circuits rather than digital circuits are examined. >

PROPAGATION DELAY IN HIGH SPEED SILICON BIPOLAR AND GaAs HBT DIGITAL CIRCUITS

Abstract: The needs for multi-gigabits/second digital electronics in advanced lightwave systems have motivated R & D for the next generation of high speed bipolar technology. The speed of the digital circuit may be estimated from the propagation delay of the logic gate. We discuss physics of the delay and show that it is fundamentally limited by the time needed for turning on (off) a transistor and by the time for charging (discharging) of capacitances in the circuit. We present a large-signal theory based on a charge-control model for the calculation of these limits. The results obtained for emitter coupled logic and current mode logic are used to analyze current technologies of silicon bipolar and GaAs HBTs.

Built-in testing of integrated circuit wafers

Abstract: Production testing of a digital circuit requires the generation of a sequence of tests and their application to the circuit being tested. Currently, in test application, the output of the circuit under test is compared to a known correct output for each test. The method has some drawbacks likely to become more critical in the near future. In homogeneous systems of identical integrated circuits of silicon wafers, testing can be done in another way, i.e. by applying a common test to several processing elements at once and comparing the results produced by them. The authors analyze such schemes and show that they are inherently as accurate as current methods that use assumed correct results for production testing. Since this approach could allow wafers to be tested for production faults significantly more quickly than by using a probe tester, the results indicate that it can provide an attractive alternative to current methods for production testing of silicon wafers. >

A multichannel digital demodulator for LVDT/RVDT position sensors

Abstract: The architecture, VLSI implementation, and test results for a mixed analog and digital multichannel demodulator used with linear/rotary-variable-differential-transformer (LVDT/RVDT) position sensors are presented. The monolithic multichannel demodulator has four regular demodulation channels and a fifth channel for system tests. Each channel has a first-order Sigma - Delta analog-to-digital converter implemented in switched-capacitor circuits, and a dedicated digital demodulator with a 32-b word length. The outputs of the analog-to-digital converters are digitally demodulated, down-sampled, and filtered. The digital demodulator uses an adaptive AM demodulation algorithm based on prediction techniques. Simulation of the digital circuitry as well as a placement and routing of the mixed signal circuitry was done using a bit-serial compiler. The design was fabricated in a 1.2- mu m p-well bulk CMOS process and contains 83000 transistors in a die size of 325*330 mil/sup 2/. Test results show that absolute accuracies of +or-0.2% of full scale are achieved without calibration. >

Digital MMIC/analog MMIC structures and process

Abstract: A transmit/receive module including digitally controlled analog circuits is described. The digital circuits use a logic family adapted for use with analog monolithic integrated circuits. The disclosure also describes a preferred process to provide digital and analog microwave circuits on a common semiconductor substrate.