Showing papers on "Electronic packaging published in 2001"

Silicon piezoresistive stress sensors and their application in electronic packaging

Abstract: Structural reliability of integrated circuit (IC) chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, operating temperatures, and the use of a wide range of low-cost packaging materials. A powerful method for experimental eval- uation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezore- sistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented. In the absence of die failure, packaging-induced stresses result in changes in the parametric performance of circuitry on the die, and the theory discussed here can be used to predict such changes. Index Terms—Electronic packaging, piezoresistive, stress sensor, test chip.

Precision spray processes for direct write electronic components

Abstract: This invention combines the precision spray process with in-flight laser treatment in order to produce direct write electronic components. In addition to these components, the process can lay down lines of conductive, inductive, and resistive materials. This development has the potential to change the approach to electronics packaging. This process is revolutionary in that components can be directly produced on small structures, thus removing the need for printed circuit boards.

Failure modes and FEM analysis of power electronic packaging

Abstract: The development of power electronics technology is driven by the insatiate demand to control electrical power. The new power electronics devices reduce the volume of the converters by three to four orders of magnitude compared to their mercury arc predecessor. And the turn-on and turn-o0 time has decreased from milliseconds to the microseconds and even nanoseconds, depending on power level. The power range commanded by converters now extends from micro-VA to several hundreds of mega-MVA. Among the new power devices, insulated gate bipolar transistor (IGBT) devices are being more accepted and increasingly used in traction application such as locomotive, elevator, tram and subway. Thus the long-term reliability of IGBT is highly demanded. In this paper the failure modes of power electronics devices especially IGBTs are reviewed. A FEM analysis of a multilayered IGBT packaging module under cyclic thermal loading is presented.? 2001 Elsevier Science B.V. All rights reserved.

Packaging of electro-microfluidic devices

Abstract: A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

An overview of solder bump shape prediction algorithms with validations

Abstract: The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range.

Silicon interposer with optical connections

Abstract: An improved electronic packaging assembly is provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The electronic packaging assembly includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. The electronic packaging assembly also includes at least one, or a number of, semiconductor chips located on opposing surfaces of the silicon interposer. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. An optical detector and an optical emitter are located on the silicon interposer and couple the silicon interposer to a fiber optical network.

Electronic packaging materials and their properties

Abstract: Electronic Packaging Materials and Their PropertiesElectronic Equipment Packaging TechnologyReliability and Failure of Electronic Materials and DevicesSpringer Handbook of Electronic and Photonic MaterialsModeling, Analysis, Design, and Tests for Electronics Packaging beyond MooreElectronic PackagingPortable Consumer ElectronicsSemiconductor PackagingAdvanced Electronic PackagingPower Electronic PackagingMechanical Analysis of Electronic Packaging SystemsFood PackagingMicroelectromechanical SystemsHigh Temperature ElectronicsElectrical Conductive Adhesives with NanotechnologiesElectronic Packaging of High Speed CircuitryPrinted Circuit Board Materials HandbookElectronic Packaging Materials and Their PropertiesNano-BioElectronic, Photonic and MEMS PackagingAdvanced Materials for Thermal Management of Electronic PackagingModeling and Simulation for Microelectronic Packaging AssemblyMaterials for Electronic PackagingMaterials for Advanced PackagingHandbook of Electronics Manufacturing EngineeringElectronic Packaging for High Reliability, Low Cost ElectronicsWide Bandgap Power Semiconductor PackagingThe Electronic Packaging HandbookMaterials for High-Density Electronic Packaging and InterconnectionHarsh Environment ElectronicsMaterials for High-Temperature Semiconductor DevicesAdvanced Adhesives in ElectronicsNanopackagingElectronic CompositesEssentials of Electronic PackagingElectronic Packaging Materials and Their PropertiesElectronic Packaging Materials and Their PropertiesNanopackagingElectronic Packaging and Interconnection HandbookMicrowave and Millimeter-Wave Electronic PackagingAdvanced Electronic Packaging Materials: Volume 167

ACA bonding technology for low cost electronics packaging applications – current status and remaining challenges

Abstract: Anisotropically Conductive Adhesives (ACAs) have been used in electronics packaging for over a decade on glass substrates, and more recently in contactless smart‐card module assembly and for bare chip attach on flexible and rigid substrates. Summarises various technologies used in connection with ACA joining. A summary of our understanding of the electrical, thermal, physical, chemical, environmental and cost behaviours of ACAs in conjunction with various packaging applications is elaborated. Finally, future research areas and remaining issues are pointed out.

Three-dimensional flip-chip on flex packaging for power electronics applications

Abstract: We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM.

Current and future miniature refrigeration cooling technologies for high power microelectronics

Abstract: Utilizing refrigeration may provide the only means by which future high-performance electronic chips can be maintained below predicted maximum temperature limits. Widespread application of refrigeration in electronic packaging will remain limited until the refrigerators can be made sufficiently small so that they can be easily incorporated within the packaging. A review of existing microscale and mesoscale refrigeration systems revealed that only thermoelectric coolers (TECs) are now commercially available in small sizes. However, existing TECs are limited by their maximum cooling power and low efficiencies. A simple model was constructed to analyze the performance of both existing and predicted future TECs in an electronic packaging environment. Comparison with the cooling provided by an existing high-performance fan shows that they are most effective for heat loads less than approximately 100 W, but that for higher heat loads, fan air cooling actually yields a lower junction temperature. If the efficiency of future TECs, as characterized by ZT/sub room/, where Z is the figure of merit and T/sub room/ is room temperature, can be increased from the present value of /spl sim/0.8 to 2 or even 3, TEC performance improves dramatically, thus making them competitive for many electronic applications. Finally, one unanticipated result of the model was the realization that the thermal resistance between the refrigerator and the chip is not as critical as the thermal resistance between the refrigerator and the ambient air.

Silicon on sapphire CMOS for optoelectronic microsystems

Abstract: we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues.

Experimental Damage Mechanics of Microelectronics Solder Joints under Concurrent Vibration and Thermal Loading

Abstract: Concurrent vibration and thermal loading is commonly encountered in the service life of electronic packaging, such as in automotive, airplane, military and mobile electronic devices. Solder joint r...

Bump-less interconnect for next generation system packaging

Abstract: A concept of bump-less interconnect for the next generation system packaging was proposed previously. Here the bump-less interconnect is defined as an interconnect of a size below 10 /spl mu/m pitch between chip and substrate, or between chip and chip. Such ultra-fine pitch interconnection will be necessary to realize high speed systems such as chip on chip or 3-D configuration for highly integrated multi-chip system in packaging. Two requirements are considered: Firstly, a transmission structure called stacked-pair line will be adopted in the bus-line in boards, and secondly, the surface activated bonding, SAB, is used to enable such ultra-high dense interconnection. A model, which is called IMSI-model 2000, is presented as an example of high speed CPU-memory.

Experimental equivalent-circuit modeling of SMD inductors for printed circuit applications

Abstract: An understanding of the high-frequency parasitic and packaging effects of passive surface-mounted devices (SMDs) can be gained from equivalent-circuit characterization of the device. We develop a circuit model which accurately characterizes the nonideal behavior of SMD inductors mounted on a printed circuit board (PCB), considering the device packaging and the interaction between board layout and component parasitics. The model is valid over a wide frequency band up to the first resonance of the inductor. The equivalent-circuit parameters are extracted in closed form from an accurate measurement of the S-parameters of the board-mounted SMD inductor, without the necessity for cumbersome optimization procedures normally followed in RF circuit synthesis. This procedure of measuring the component in its designed PCB environment is referred to as extrinsic characterization, in contrast to the conventional intrinsic characterization employed in RF bridges and LCR meters, which does not include the board layout effects. The developed closed-form model can be directly incorporated in commercial CAD packages, and thus, it simplifies the analysis of electromagnetic field behavior in PCBs, such as prediction of radiated emissions, signal integrity, and EMI.

Advanced composites and other advanced materials for electronic packaging thermal management

Abstract: A variety of new advanced composites and other advanced materials are now available which provide great advantages over conventional materials for thermal management and microelectronic packaging, including: extremely high thermal conductivities (over three times that of copper); low, tailorable coefficients of thermal expansion; weight savings of up to 80%; size reductions of up to 65%; extremely high strength and stiffness; reduced thermal stresses; increased reliability; simplified thermal design; possible elimination of heat pipes; low cost, net shape fabrication processes; potential cost reductions. Composites and other advanced materials are in a state of continual development that undoubtedly will result in improved and new materials providing even greater benefits. The number of production applications is increasing rapidly, and these new materials are well on their way to becoming the 21st century materials of choice for thermal management and electronic packaging. This paper provides an overview of advanced composites and other materials used in thermal management and electronic packaging, including properties, applications and future trends. The focus is on materials having thermal conductivities at least as high as those of aluminum alloys. We also examine future trends.

Flexible tape electronics packaging

Abstract: To decrease the weight and the thickness, and to increase the flexibility, of an electronics package, the package includes an integrated circuit (IC) mounted on a flexible tape substrate. In one embodiment, an IC is mounted on a flexible tape substrate using a ball grid array arrangement; however, other arrangements, including lead bonding, can be used. The flexible tape substrate can comprise conductive traces, vias, and patterns of lands on one or more layers. Methods of fabrication, as well as application of the flexible tape package to an electronic assembly, an electronic system, and a data processing system, are also described.

Stacked thin dice packaging

Abstract: This paper reports on a developed stacking method to produce a small volume three-dimensional package. The first part of the 3/sup rd/ dimension is tackled by reducing package thickness and also the stand-off height. The steps came through thinning dice, using a thin interposer, and to stack the components. The thickness of the used ICs was 90 /spl mu/m, whereas typically thicknesses are around 250-300 /spl mu/m. Thin dice were connected through eutectic solder bumps on thin aramid epoxy substrates. The package was studied with the finite element method (FEM) using three-dimensional (3-D) models and the Ansys program. The average plastic work in the solder bump was used to define the reliability of the structure. Structures with one to four layers are compared. In current flip-chip assemblies, rigidity assists good electrical performance and reliability. Reducing the IC thickness below 100 /spl mu/m creates new challenges for handling, interconnecting, reliability and design. These tasks have been addressed in this study. The designed circuits for the above tests have been characterized and more details of the results are presented. Further progress in density increase has been achieved by stacking layers of flexible substrate and thin die on top of each other. For this work, the first level connection has been flip-chip bonding. The goal was to develop a method to produce modules on a small scale to verify the feasibility of various System-in-Package (SiP) solutions. The method has been tested using thin dice, mainly daisy chain. Devices are miniaturized to be more comfortable to carry; this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Size reduction of electronics has set a challenge for packaging and provided the motivation to verify emerging technologies.

Micromachined, flip–chip assembled, actuatable contacts for use in high density interconnection in electronics packaging

Abstract: Using flip–chip assembly, micromachined contacts can be used to create a high density, actuatable electronics packaging technology. Internal residual stress is used to press bimorph beam connectors upwards against a device chip. The connectors’ actuation behavior is described, including appropriate mathematical models. The electrostatically actuated beams will disconnect when driven by a 53 V signal and will reconnect when voltage falls below 43 V. Analytic models, which account for the non-linearity present in a curved cantilever beam, are presented. When switching signals, reconnection occurs in as little as 5.8 μs, disconnection occurs in as little as 4.0 μs. A microconnector’s current carrying capability can be as high as 285.3 mA and its maximum power dissipation as high as 1.47 W.

MEMS sensor packaging using LTCC substrate technology

Abstract: Low Temperature Cofired Ceramic (LTCC) material can be used as a reliable multilayer substrate material for silicon based MEMS component packaging due to many benefits like hermeticity, good match of thermal expansion coefficient (TCE) to silicon to minimise packaging-induced thermomechanical stresses, and the possibility to make cavities into the structure. The applicability of LTCC technologies for MEMS packaging is described in this paper. A review of the technologies used in making LTCC modules, such as substrate manufacturing, interconnecting, sealing and protection, and the benefits of LTCC for MEMS packaging is presented. Also examples on the use of LTCC technology for MEMS sensor packaging are discussed.

Improving signal integrity in circuit boards by incorporating absorbing materials

Abstract: Electrical signals that propagate through vias between layers of metal planes in circuit boards will generate radial waves that are guided by the planes. Multiple reflections of these parallel plate waves from the edges of the circuit board will cause resonances that greatly increase the effective impedance between the two planes at the resonant frequencies. Such resonances are highly undesirable for operation of high performance electronic packaging systems since they degrade signal qualities, increase crosstalk level and enhance simultaneous switching noise. In this paper we show that the magnitude of the resonances can be greatly reduced by incorporating an absorbing material between the metal planes at the perimeter of the circuit board. As a result the signal integrity of the system is improved. By using absorbing materials whose loss depends upon magnetic rather than electric effects, it is possible to choose materials whose resistivity is of the order of 10/sup 12/ ohm-cm, making it possible to place the materials directly between power and ground planes without introducing any DC current leakage. These materials are available commercially in flexible and hard, dense forms and can be chosen to enhance losses at either the UHF band or various microwave frequency bands to accommodate different needs. Results of theoretical computation are compared with experiments performed on test boards characterized using a vector network analyzer between 50 MHz and 6 GHz. Significant reduction in input impedance of the test structure at resonance frequencies is obtained, which shows the effectiveness of the proposed method and the accuracy of the calculation method. The paper also evaluates several ways of applying the lossy material.

Dimple-array interconnect technique for packaging power semiconductor devices and modules

Abstract: This paper reports a simple non-wire bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Solder bumps and dimpled metal sheets that are capable of carrying large currents are utilized for interconnecting power chips. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced dc resistance and parasitic noises, improved heat dissipation and thermo-mechanical reliability, and lowered processing complexity. This technique also offers a potential approach for packaging power electronics modules.

Precision Alignment Packaging for Microsystems With Multiple Fluid Connections

Abstract: The application of microfluidic Microsystems to solve real world problems depends on effective packaging techniques. In this paper, we report on packaging methods that allow the connection of multiple fluid lines to a microfluidic chip. Eight different fluid connections are made in a 5 mm square area (100 connections possible) using a flip chip aligner/bonder with precise alignment on the order of 10 microns between holes (1 micron precision possible). The critical fluid connections are made using 0.002 inch thick double sided adhesive tape and are shown to hold greater than 20 atm of pressure without leaking. The packaging flow manifold and assembly methods are suitable for inexpensive mass production and are compatible with existing electronics packaging technologies.