Showing papers on "Electronic packaging published in 2022"

Advances on Thermally Conductive Epoxy‐Based Composites as Electronic Packaging Underfill Materials—A Review

Abstract: The integrated circuits industry has been continuously producing microelectronic components with ever higher integration level, packaging density, and power density, which demand more stringent requirements for heat dissipation. Electronic packaging materials are used to pack these microelectronic components together, help to dissipate heat, redistribute stresses, and protect the whole system from the environment. They serve an important role in ensuring the performance and reliability of the electronic devices. Among various packaging materials, epoxy‐based underfills are often employed in flip‐chip packaging. However, widely used capillary underfill materials suffer from their low thermal conductivity, unable to meet the growing heat dissipation required of next‐generation IC chips with much higher power density. Many strategies have been proposed to improve the thermal conductivity of epoxy, but its application as underfill materials with complex performance requirements is still difficult. In fact, optimizing the combined thermal–electrical–mechanical–processing properties of underfill materials for flip‐chip packaging remains a great challenge. Herein, state‐of‐the‐art advances that have been made to satisfy the key requirements of capillary underfill materials are reviewed. Based on these studies, the perspectives for designing high‐performance underfill materials with novel microstructures in electronic packaging for high‐power density electronic devices are provided.

Interleaved Planar Packaging Method of Multichip SiC Power Module for Thermal and Electrical Performance Improvement

Abstract: Double-sided cooling based on planar packaging method features better thermal performance than traditional single-sided cooling based on wire bonds. However, this method still faces thermal and electrical challenges in multichip SiC power modules. Specifically, one is severe thermal coupling among parallel bare dies, and the other is unbalanced current sharing due to unreasonable layout design. This article aims to explore the potentials of SiC power devices in power module, which are higher current capability and reliability. The proposed packaging method is called interleaved planar packaging and can get rid of the optimizing contradiction between thermal and electrical performance. In this packaging method, there are two functional units: interleaved switch unit and current commutator structure. Benefited from the two units’ electromagnetic and thermal decoupling effects, the interleaved power module features low loop inductance, balanced current, low coupling thermal resistance, and even thermal distributions. A 1200 V 3.25 mΩ half-bridge SiC power module based on interleaved planar packaging is fabricated and tested to verify this method's superiority.

Microstructured BN Composites with Internally Designed High Thermal Conductivity Paths for 3D Electronic Packaging

Abstract: Miniaturized and high‐power‐density 3D electronic devices pose new challenges on thermal management. Indeed, prompt heat dissipation in electrically insulating packaging is currently limited by the thermal conductivity achieved by thermal interface materials (TIMs) and by their capability to direct the heat toward heat sinks. Here, high thermal conductivity boron nitride (BN)‐based composites that are able to conduct heat intentionally toward specific areas by locally orienting magnetically functionalized BN microplatelets are created using magnetically assisted slip casting. The obtained thermal conductivity along the direction of alignment is unusually high, up to 12.1 W m−1 K−1, thanks to the high concentration of 62.6 vol% of BN in the composite, the low concentration in polymeric binder, and the high degree of alignment. The BN composites have a low density of 1.3 g cm−3, a high stiffness of 442.3 MPa, and are electrically insulating. Uniquely, the approach is demonstrated with proof‐of‐concept composites having locally graded orientations of BN microplatelets to direct the heat away from two vertically stacked heat sources. Rationally designing the microstructure of TIMs to direct heat strategically provides a promising solution for efficient thermal management in 3D integrated electronics.

Interleaved Planar Packaging Method of Multichip SiC Power Module for Thermal and Electrical Performance Improvement

Abstract: Double-sided cooling based on planar packaging method features better thermal performance than traditional single-sided cooling based on wire bonds. However, this method still faces thermal and electrical challenges in multichip SiC power modules. Specifically, one is severe thermal coupling among parallel bare dies, and the other is unbalanced current sharing due to unreasonable layout design. This article aims to explore the potentials of SiC power devices in power module, which are higher current capability and reliability. The proposed packaging method is called interleaved planar packaging and can get rid of the optimizing contradiction between thermal and electrical performance. In this packaging method, there are two functional units: interleaved switch unit and current commutator structure. Benefited from the two units’ electromagnetic and thermal decoupling effects, the interleaved power module features low loop inductance, balanced current, low coupling thermal resistance, and even thermal distributions. A 1200 V 3.25 mΩ half-bridge SiC power module based on interleaved planar packaging is fabricated and tested to verify this method's superiority.

Development of LED Package Heat Dissipation Research

Abstract: LEDs are widely used in medicine, navigation and landscape lighting. The development of high-power LED is a severe challenge to LED heat dissipation. In this review, packaging technology and packaging structure are reviewed in terms of the thermal performance of LED packaging, and related technologies that promote heat dissipation in LED packaging are introduced. The design of three components to enhance heat dissipation in LED packaging is described: substrate, lens and phosphor layer. By conducting a summary of the technology and structure of the package, the defects of LED package technology and structure are deeply investigated, and the package is prospected. This has reference value for the heat dissipation design of the LED package and helps to improve the design and manufacture of the LED package.

Panel Level Packaging – Where are the Technology Limits?

Abstract: Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face- down have reached maturity and are introduced in high volume manufacturing. For Fan-out Wafer Level Packaging (FOWLP) clear application trends and technology roadmaps do exist. These range from low density core technology for e.g. RF or PMIC (power management IC) packaging over high density application processor packaging to ultra-high-density applications for networking servers etc.. For panel level packaging it is still not fully clear if the same performance can be achieved as on wafer level as larger process / panel sizes may have higher challenges in process control, accuracy and consistency, material and equipment or handling.Main driver for moving to panel level packaging is of course lowering the packaging cost. More packages can be processed in parallel and panel formats have a much better area utilization (ratio between panel/wafer size and package size) than round wafer shapes. Also, environmentally PLP is advantageous by e.g. lower waste and smaller carbon footprint. However, for both aspects processes with sufficiently high yield are required. This is especially true for FOWLP/PLP RDL last processes as a failure in the RDL will also lead to a loss of packaged die(s).This paper describes current technology developments to access the limits of the panel level packaging technology. Warpage, die shift and fine line capabilities are the main topics here. To better understand the compression molding process as the technological basis of the reconfigured panel and its influence on warpage and die shift a dedicated sensor mold tool has been developed. By integration of temperature, pressure, dielectric and fiber Bragg grating sensors the flowing and curing behavior of epoxy molding compound can be studied in-situ. Results will support process simulations for warpage prediction and more accurate die shift compensation.For large panel processing an adaptive patterning approach might be needed anyhow to achieve a high yield. Here the combination of an intelligent assembly strategy for high speed and sufficient accuracy, capabilities to measure each die position and a maskless lithography process adapting the redistribution layer (RDL) to each die position may lead to a cost-effective high yield process.In addition, a clear trend towards finer lines and spaces as well as smaller via diameters is also demanded for large panel RDL processes. Process developments towards 2 μm lines and spaces and via shrinking on 610x457 mm2 (24"x18") panels are shown including material and process options.In summary this paper will show current PLP technology developments for future high-end applications and will cover at the same time economic and environmental aspects.

Investigations on High-Power LEDs and Solder Interconnects in Automotive Application: Part I—Initial Characterization

Abstract: Thermo-mechanical reliability is one major issue in solid-state lighting. Mismatches in the coefficients of thermal expansion (CTE) between high-power LED packages and substrates paired with temperature changes induce mechanical stress. This leads to a thermal degradation of LED modules by crack formation in the solder interconnect and/or delamination in the substrate, which in turn increases junction temperature and thus decreases light output and reduces lifetime. To investigate degradation and understand influence of LED package design and solder material, a reliability study with a total of 1800 samples − segmented in nine LED types and five solder pastes − is performed. First of all, in this paper a state-of-the-art review of high-power LED packages is performed by analyzing and categorizing the packaging technologies. Second, the quality inspection after assembly is realized by transient thermal analysis (TTA), scanning acoustic microscopy (SAM) and X-ray. For TTA, a new method is introduced to separate the thermal resistance of the LED package from solder interconnect and substrate by applying the transient dual interface method (TDI) on samples with different solder interconnect void ratios. Further measurement effort is not required. The datasheet values for thermal resistance are verified and the different LED package types are benchmarked. The void ratio of the solder interconnects is determined by X-ray inspection combined with an algorithm to suppress disruptive internal LED package structures. TTA and TDI revealed that initial thermal performance is independent of solder paste type and that voiding is more critical to smaller LED packages. In addition, lower silver proportion in the paste is found to increase voiding. SAM is less sensitive for initial void detection than X-ray, but it’s applied to monitor crack propagation while aging in combination with TTA. The results of the reliability study, i.e., the crack growth under temperature shock test for the different SAC solders, will be presented in a second independent paper.

Structure and Properties of Au–Sn Lead-Free Solders in Electronic Packaging

Abstract: The requirements for electronic devices in high-temperature environment such as avionics and automotive have promoted the development of high-temperature solders. The Au–20Sn solder, which is one of the hot topics of the current research in the field of electronic packaging, is widely used in flip-chip, light-emitting diode and hermetic package fields because of its good creep resistance, corrosion resistance and flux-free soldering. Recent research about the microstructure, wettability, interfacial intermetallic compounds, and mechanical properties of Au–20Sn solder were reviewed. This paper focuses on the interfacial reaction of Au–20Sn with different substrates and the mechanical properties of Au–20Sn solder joints. In addition, the current research shortages of Au–20Sn solders and the development directions are presented.

Pressureless Sintered-Silver as Die Attachment for bonding Si and SiC Chips on Silver, Gold, Copper, and Nickel Metallization for Power Electronics Packaging: The Practice and Science

Abstract: Low-temperature silver (Ag) sintering is emerging as a cutting-edge die-attach technology for power electronics packaging. However, the industry still has concerns about completely accepting this technology. One of the reasons is a lack of knowledge about the mechanism and process of sintered silver bonding on various metallization. Before, we reported a preliminary assessment of the die-shear strength and microstructures of Si dummy device attached on Ag, Au, and Cu metallization. This research will go deeper into the practice and science of attaching Si and SiC devices with sintered-Ag on substrates with up to seven most widely used metallizations, including electroplated Ag, Ni/Au, and Ni, electroless-plated Ni(P)/Ag, Ni(P)/Au, and Ni(P), and native Cu on DBC substrate. All sintered-Ag die-attach were pressureless in the air at temperatures ranging from 220 °C to 300 °C. The mechanical, electrical, and thermal parameters, as well as the microstructural analyses, were assessed. The purpose of this research is to gain a better understanding by: 1) discussing effects of devices and substrate metallizations on the mechanical, electrical, and thermal characteristics; 2) reviewing fundamental mechanisms of interfacial adhesion for sintered-Ag bonding, and 3) providing practical considerations for developing Si and SiC sintered-Ag die-attaching profiles on the widely used substrate metallization.

Investigation on Package Warpage and Reliability of the large size 2.5D Molded Interposer on Substrate (MIoS) Package

Abstract: 2.5D silicon interposer integration package technology has been developed for high-end applications such as AI, datacenter, server, etc. In order to achieve higher performance, the types and number of integrated chips are gradually increasing. The package size is also increasing due to more number of chips to be integrated. As the package size increases, various technical challenges are accompanied by such as molded chip warpage, package level reliability or package warpage. In the previous study, we introduced a 2.5D package structure called Molded Interposer on Substrate (MIoS) which is composed of 2-logic and 8-HBM devices on 2800mm2 size Si interposer. The package body size of 8-HBM MIoS package is 85x85mm2. In this study, package warpage and reliability of large size package were investigated. Package warpage is caused by the CTE mismatch between organic substrate and molded interposer chip which is composed of Si devices. To compensate the package warpage induced by the CTE mismatch, a stiffener structure was attached. The warpage shape caused by CTE mismatch was investigated, and stiffener structure, stiffener material properties and adhesive material properties were studied to effectively compensate for the package warpage. The effect of each parameter on the package warpage was investigated through experiments and package warpage expectation model was developed. Also the package level reliability verification was performed for various structures controlling the package warpage. Through this study, package warpage control technology of large size 2.5D package with various sizes and configurations was achieved.

Shock and impact reliability of electronic assemblies with perimeter vs full array layouts: A numerical comparative study

Abstract: Abstract This study aims to assess the effect of the solder joint array layouts, including full and peripheral designs, on the mechanical response and reliability of electronic packages subjected to shock and impact loadings. Linear and nonlinear finite element simulations using the global-local modeling technique are employed to perform the analysis. Several peripheral array configurations are considered and compared to the full array systems. The results showed that, for optimum electronic package designs in terms of reliability and cost, it is highly recommended to use peripheral packages having three or four rows of solder interconnects in electronic systems under shock and impact loadings.

Synthesis of tetra(epoxy)-terminated open-cage POSS and its particle thermo-crosslinking with diphenols for fabricating high performance low-k composites adopted in electronic packaging

Abstract: Polyhedral oligomeric silsesquioxanes (POSSs) are ideal particles to reduce the dielectric constant (k) and loss (tan δ ) values of resin matrixes for electronic packaging, but greatly limited by its finite addition due to phase-separation. Herein, tetra(epoxy)-terminated open-cage TG-POSS was synthesized and utilized as a unique building block to crosslink with bisphenol A or hexafluoro-bisphenol A, respectively, for the preparation of novel high performance low-k composites (POSS/BPA or POSS/FBPA). Results reveal that such rational design endows these two materials with homogeneous hybridization even at high POSS loading (>72.0wt%), which is the main reason for superior dielectric, thermal and hydrophobic properties compared with counterparts reported previously. Especially, fluorinated POSS/FBPA shows the lowest k value of 2.38, lowest tan δ value of 0.008, highest initial decomposition temperature of 396.1 °C and largest water contact angle of 117.0°, under the extra-contribution of trifluoromethyl units. In addition, its well-dispersed, moderate-crosslinked and rigid-flexible polymer network also leads to outstanding mechanical properties (elongation at break of 3.50% and modulus of 2.75 GPa) for practical applications. Summarily, this work highlights a useful strategy to fabricate high performance low-k composites with high POSS content, which is not only potential for advanced microelectronic industry but also instructive for academic fields. • A tetra(epoxy) TG-POSS with inorganic open-cage structure was synthesized. • TG-POSS was utilized to thermo-crosslink with diphenols for novel low-k composites. • The prepared composites show advanced low-dielectric and other comprehensive properties. • The superior properties are mainly attributed to the open-cages from TG-POSS. • The prepared composites have broad application prospects for electronic packaging.

Interfacial engineering of epoxy/silica nanocomposites by amino-rich polyethyleneimine towards simultaneously enhanced rheological and thermal-mechanical performance for electronic packaging application

Abstract: As electronic devices move toward miniaturization and high-degree integration, it becomes imperative to use nano-sized silica as a reinforcing filler for epoxy resin in modern electronics packaging industries. However, the use of silica nanoparticles (SNPs) brings about new challenges in filler dispersion and in the balance between the rheology and thermal mechanical performance of epoxy nanocomposites. This study presents a novel strategy aiming to address the above challenges by interface engineering with amino-rich branched polyethyleneimine (PEI) polymer molecules through a facile self-assembly process. This not only enables a considerable decrease (by 79.7%) in viscosity accompanied by a significant improvement in viscosity stability (only 2.7 times increase after 24 h) but also leads to a further CTE reduction of 4.8 ppm/ ° C (equivalent to the effects of around 10 wt% SNPs) relative to the SNPs. This work offers a new direction and efficient approach to develop high-performance epoxy composites for electrical packaging applications as well as provides some fresh insights into the interface-property relationships. Interfacial engineering by surface modification of silica nanoparticles (SNPs) with amino-rich branched polyethyleneimine (PEI) polymer molecules through a facile self-assembly process is developed to simultaneously improve the rheological and thermomechanical properties of SNPs/epoxy nanocomposites for electrical packaging applications.

Bonding formation and gas absorption using Au/Pt/Ti layers for vacuum packaging

Abstract: In this study, we developed a metal multilayer that can provide hermetic sealing after degassing the assemblies and absorbing the residual gases in the package. A package without a leak path was obtained by the direct bonding of the Au/Pt/Ti layers. After packaging, annealing at 450 °C caused thermal diffusion of the Ti underlayer atoms to the inner surface, which led to absorption of the residual gas molecules. These results indicated that a wafer coated with a Au/Pt/Ti layer can provide hermetic sealing and absorb residual gases, which can simplify vacuum packaging processes in the electronics industry.

Packaging applications of polymer-graphene composites

Abstract: The area of graphene-based polymer composites has seen numerous advancements with the isolation of a single layer of graphene from a stock of bulk graphite. It consists of superior mechanical, electrical, and thermal. Graphene when combined with polymers results in composites within nano regime with improved characteristics such as gas permeability, better thermal response, mechanical strength and modulus, electrical conductivity etc. makes it a superior material of choice for use in the areas of food and electronic packaging. The food and electronic packaging markets are expected to grow at compounded annual growth rate of 7% and 18% respectively due to inflated volumes of production. The increased use of bioplastics in packaging is the trend going forward with issues regarding proper use and disposal of conventional packaging plastics after use. The increase in properties with a multifunctional effect makes it the material of choice in packaging. Also, the electrical conductivity characteristics such as EMI shielding, lead-free green soldering materials, etc. makes it suitable as a material for electronics packaging. The scope of work covered in the research for the use of graphene-polymer nanocomposites in packaging (food and electronics) is very vast. The authors have made an honest attempt toward covering both the important aspects and recent developments.

A study of large area bonding technologies and their application in electronic industry

Abstract: As high-power electronic devices are in a rapid developing speed, the topic of large area bonding in electronics emerged in recent years. The needs such as die-attach for large area chip (>10mm x 10 mm), high thermal dissipation power baseplate/heatsink attachment (connect devices to heatsink/baseplate) lead to the demand for reliable large area bonding technology with excellent thermal performance. However, the current adapted solutions are with various advantages and disadvantages. Epoxy-based adhesive is a versatile technology with excellent processibility, whereas the low thermal conductivity and reliability due to the high organic content in various cases cannot meet application requirements. The other commonly adopted technology is Sn-based solder paste technology, which is matured and cost effective with higher thermal performance. On the other hand, the low melting point and relatively high process temperature limits the packaging design and system reliability performance. Additionally, although the thermal conductivity is much better than epoxy-based adhesive, for high power application, it is not sufficient. Furthermore, in the past years, silver sintering has become an emerging solution for large area bonding, especially for high power and automotive applications due to the high thermal conductivity and reliability it can offer. Nonetheless, cost and many technical difficulties are existing that limits the adoption of this novel technology, such as relatively high process temperature, high mechanical pressure needed, voiding channels, and pick and place of the parts. Therefore, it seems of vital importance to have a comprehensive analysis of the current solutions to make proper suggestions of suitable applications. Moreover, for novel technology, such as silver sinter, the technology gaps and scientific challenges should be identified for accelerating the adoption.In this study, currently adopted large area bonging technologies and their merits and demerits are reviewed and discussed. The most suitable applications for each technology are suggested. In addition, the current technology gaps of silver sintering for large area bonding are shown, and the scientific challenges to fill in these gaps are presented as well.

Direct flip-chip bonding of bare dies to polypropylene-coated paper substrates without adhesives or solders

Abstract: Abstract Paper-based electronics is an emerging concept with the prospect of developing recyclable, low cost, flexible, and green products such as paper displays, smart labels, RFID tags, smart packages, electronic magazines, biological and medical devices. Compared to conventional printed circuit board (PCB) materials, utilizing paper as an electronics substrate has both physical and chemical challenges. Nowadays, the integration of components on papers are mainly conducted using adhesives [such as anisotropic conductive paste (ACP), isotropic conductive paste (ICP), and non-conductive pastes (NCP)] or low-temperature solders. The application of adhesives and solders in a roll-to-roll fabrication line of papers requires an additional dispensing or printing unit, which has its own drawbacks. Therefore, alternative approaches such as pre-applied adhesive films either on bare dies or papers can gain significant attention. In this study, by exploiting the unique properties of a paper coating material (i.e., polypropylene) as a non-conductive adhesive, it was shown that direct flip-chip bonding of the bare dies and devices could be successfully performed on paper without using any additional adhesives or solders. The electrical and mechanical performance of the flip chip-bonded dies on the polypropylene-coated paper substrate were assessed utilizing daisy-chain contact resistance measurement and die-shear analysis, respectively. Moreover, for an RFID tag application, RFID chips were flip chip bonded to the coated papers and functional tests via NFC communication were also successfully exerted. It was concluded that the polypropylene film on the paper can be considered as an intrinsic NCP layer for flip-chip integration of bare dies.

Anisotropic Highly Conductive Joints utilizing Cu-Solder Microcomposite Structure for High-Temperature Electronics Packaging

Abstract: • A new anisotropic microcomposite (AMC) joint utilizing a lotus-type porous Cu (LPC) sheet and Sn-based solder was developed. • A simple reflow process allowed joint formation via infiltration of the molten solder into the LPC sheet. • AMC joints exhibited thermal conductivity of 142.4 W/m·K, 2.5 times higher than that of the solder. • A stable shear strength of > 46 MPa was achieved after the aging test at 200 °C for 1008 h. • LPC utilization exploited the full potential of the solder for high-temperature electronic applications. The miniaturization of power conversion systems requires high-power density operation of power modules, causing the heat-density increase. Therefore, it is essential to develop bonding technology to realize highly thermally conductive and reliable high-temperature joints. In this study, we propose a novel anisotropic microcomposite (AMC) joint that integrates a lotus-type porous Cu (LPC) sheet and Sn-based solder for high-temperature electronic applications. The AMC joint was successfully fabricated by infiltrating the molten solder into the unidirectional pores of the LPC sheet during a simple reflow process. Steady-state thermal conductivity measurements for a uniquely designed specimen revealed its equivalent thermal conductivity (142.4 W/m·K), 2.5 times higher than the solder. Finite element simulations supported its excellent thermal performance by investigating the heat flux distribution and thermal conductivity prediction that utilize a three-dimensional image-based constructed model. In addition, the aging test at 200 °C for 1008 h clarified a stable shear strength of over 46 MPa. This indicates a reliable mechanical performance at 200 °C, which is only 20 °C below the melting point of the solder. These experimental and numerical studies proved the potential of the novel joint as a high-temperature electronics joint and offered possible mechanisms for its thermal and mechanical property enhancement.

Influence of Ball Grid Array Design Parameters on Solder Joint Reliability

Abstract: Ball grid array (BGA) package is widely used in electronic packaging. This type of package can accommodate high I/O in the small form factor package size compared to the quad-flat package (QFP) and quad-flat no-lead (QFN). Due to its function to electrically connect the package substrate to the printed circuit board (PCB), it is important to ensure the 2 ^nd level interconnect is reliable against cyclic thermo-mechanical load. Ever-increasing functional density in microelectronic components requires a continuous redesign of packaging technology. Characteristic attributes are form factor, pin count, pitch, power density, diverse application and harsh environment. Packaging engineers have to ensure new product designs will act according to specifications and will survive in the field for the targeted market. The interconnection of the semiconductor package and PCB is one of the most critical elements in the electronic control unit. A thermal mismatch between component and PCB, together with varying temperatures causes cyclic deformation and fatigue of solder interconnect. The semiconductor manufacturers apply an accelerated temperature cycling test to assess the risk for early failure in the field. To reduce the development cycle, NXP is applying virtual prototyping and testing by simulation. This allows to run extensive design studies in a relatively short time with only a few prototype builds for empirical validation. NXP has established robust simulation technics for the assessment of fatigue in solder alloys. In this paper, we want to share a design study for BGA. We will derive the significance of various design parameters concerning the solder joint reliability in a board assembly. For instance, we will assess the influence of PCB pad diameter, solder stand-off height, solder alloy materials, die sizes and package core thickness. The simulations described in this paper are done during the early design stage to ensure all NXP products are robust and reliable. To evaluate the relative failure risk between design cases, a volume average approach on the accumulated creep energy density is used. We will discuss the significance of mentioned design parameters with respect to the board-level reliability test conditions. We will provide, a few guidelines from a mechanical standpoint to mitigate solder joint bulk fatigue under board level temperature cycling (BLTC) test conditions.

A Novel Packaging with Direct Dielectric Liquid Cooling for High Voltage Power Electronics

Abstract: This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.