Showing papers on "FET amplifier published in 2001"

An autozeroing floating-gate amplifier

Abstract: We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing floating-gate amplifier demonstrates how to use continuous-time floating-gate adaptation in amplifier design.

15 nm gate length planar CMOS transistor

Abstract: Continued scaling of mainstream planar CMOS transistor technology into the deep-sub-100 nm regime is increasingly challenging but possible. In this paper, we report bulk-silicon planar CMOS transistors with the physical gate length scaled down to 15 nm. Gate delays (CV/I) of 0.29 ps for n-channel FET and 0.68 ps for p-channel FET are achieved at a supply voltage of 0.8 V. Energy-delay products are 42 pJ-ps/m for an n-channel FET and 97 pJ-ps/m for a p-channel FET, respectively. To our knowledge; these numbers are the best reported to date.

Transmitter including a composite amplifier

Abstract: A composite amplifier includes a main power amplifier (10) and an auxiliary power amplifier (12), which are connected to a load (14) over a Doherty output network (16). Filters (26, 28) are provided for pre-filtering the amplifier input signals in such a way that the signals meeting at the output of the main amplifier have essentially the same frequency dependence.

Impedance matching low noise amplifier having a bypass switch

Abstract: An impedance matching low noise amplifier (“LNA”) having a bypass switch includes an amplification circuit, a bypass switching network and a match adjustment circuit. The amplification circuit has an amplifier input and an amplifier output, and is configured to receive a radio frequency (RF) input signal at the amplifier input and apply a gain to generate an amplified RF output signal at the amplifier output. The bypass switching network is coupled to a low-gain control signal and is also coupled between the amplifier input and the amplifier output. The bypass switching network is configured to couple the amplifier input to the amplifier output when the low-gain control signal is enabled in order to feed the RF input signal through to the RF output signal. The match adjustment circuit is coupled to the low-gain control signal and the RF input signal, and is configured to couple the RF input signal to an impedance when the low-gain control signal is enabled.

Ingrated rf power sensor that compensates for bias changes

Abstract: A system for controlling a bias circuit by sensing RF amplifier output power and compensating for a dominating quiescent bias current includes an amplifier transistor and two sampling transistors. The two sampling transistors are physically smaller than the amplifier transistor, and are preferably the same size. The first sampling transistor is configured to sample the same RF input signal that is amplified by the amplifier transistor. The second sampling transistor is configured to receive and amplify only a bias network signal. The bias network associated with the transistors includes a selection of components based upon operating parameters as well as actual physical sizes of the transistors. The selection of component values in association with transistor sizes is used to enable generation of a current sensing signal that is proportional to the power level of the RF output signal generated by the amplifier transistor. The bias current to the amplifier transistor is controlled by an operational amplifier that is fed with a reference voltage and the dc bias detected by the second small transistor.

High gain wideband driver amplifier

Abstract: Methods and circuitry for implementing monolithic high gain wideband amplifiers. The invention implements an amplifier with a limiter that also performs a signal dividing function. In a specific embodiment, the limiter is designed to make available two in-phase outputs that are then used to drive two gate input lines of a combiner distributed amplifier.

A highly efficient linearized wide-band CDMA handset power amplifier based on predistortion under various bias conditions

Abstract: This paper investigates the use of amplifier linearization for performance improvement on a power amplifier developed for a wide-band CDMA (W-CDMA) system. A predistortion technique was chosen due to its compact size, which is suitable to implement in handsets. A predistorter (PD) monolithic-microwave integrated-circuit based on a heterojunction FET (HJFET) was designed and fabricated. Depending on the control voltage, the PD achieves both gain expansion and compression characteristics, which is shown to be important for compensating various amplifier nonlinearities. The power performances of an HJFET amplifier with and without a PD are compared. Due to the variation of the amplifier's responses under high and low quiescent current levels, the PD response required for optimum distortion cancellation in each case is examined. The linearized amplifier demonstrates a state-of-the-art power-added efficiency (PAE) of 57.4% under W-CDMA criteria, resulting from a 5-dB reduction in adjacent channel leakage power ratio. In addition, the use of power control in a W-CDMA system requires amplifiers with good efficiency over a wide range of output power. By combining a bias control scheme with predistortion, it is shown that a high PAE of over 40% can also be achieved for a 20 dB output power range. The improvements achieved are attributed to the alleviation of amplifier's nonlinearities after linearization.

Multi-band amplifier

Abstract: A GaAs MMIC dual-band amplifier for wireless communications is disclosed for operation at either the 800 MHz or the 1900 MHz band and it provides desired gain and input and output impedance Switching impedance networks are used at the input and output of the amplifier to provide matching input impedance and desired output impedance for operation in the two bands Switching impedance networks are also used between any successive stages of the amplifier to provide proper interstage impedance The dual band amplifier includes a bias control circuit which biases the amplifier to operate in A, B, AB or C mode The amplifier can be used for the AMPS 800 or the GSM 900 operation or any other cellular operation such as the PCS 1900 and the it can be switched between the two operations by simply applying a proper control signal to the amplifier

Experimental investigation on efficiency and linearity of microwave Doherty amplifier

Abstract: We have investigated the microwave Doherty amplifier, testing for efficiency and linearity. For the experiment, a 1.4 GHz Doherty amplifier has been implemented using a silicon LDMOSFET. The Doherty amplifier-I (a combination of a class B carrier amplifier and a class C peaking amplifier) and the Doherty amplifier-II (a combination of a class AB carrier amplifier and a class C peaking amplifier) have been compared with class B and AB amplifiers, respectively, using single-tone, two-tone, and forward-link CDMA signals. It demonstrated the superior performance of Doherty amplifiers. The results provide a topology selection guide of the CDMA base station power amplifier to achieve both linearity and efficiency enhancements.

Power amplification for parametric loudspeakers

Abstract: A power amplifier (figure 1) for a parametric loudspeaker system which utilizes switch-mode power conversion (110) to increase efficiency. The power amplifier is configured to coordinate the switching frequency of the amplifier with the carrier frequency of the parametric loudspeaker system, so a lower switching frequency may be used even though the power amplifier must amplify ultrasonic signals. The amplifier can be further optimised to counteract the reactance of the transducer load (118) at the carrier frequency.

Concurrent multi-band low noise amplifier architecture

Abstract: The present invention relates to a monolithic, concurrent multi-band low noise amplifier (LNA). The inventive LNA includes a three-terminal active device, such as a transistor with a characteristic transconductance, gm, disposed on a semiconductor substrate. The active device has a control input terminal, an output terminal, and a current source terminal. The amplifier also includes an input impedance matching network system, Zin, and an output load network. Zin simultaneously and independently matches the frequency-dependent input impedance of the three-terminal active device to a predetermined characteristic impedance at two or more discrete frequency bands. The output load network simultaneously provides a voltage gain, Av, to an input signal at the amplifier input at each of the two or more discrete frequency bands.

Linear modulation using a linear and a non-linear amplifier

Abstract: A power amplifier uses a modulation technique that varies amplitude of a drive signal and, optionally, phase angle of the drive signal. The power amplifier comprises two coupled amplifiers, a first one of which is operated saturated to produce a constant voltage output. The first amplifier is coupled to a second one of the amplifiers via a quarteer wave transmission line. The second amplifier is operated in a linear mode to deliver an output signal controlled by an amplitude-modulating signal. The amplitude modulating signal may be a bipolar modulation signal that produces both positive and negative outputs from the second amplifier that add to or subtract from the output from the first amplifier to develop at a load inpedance net output signal amplitudes varying between a minimum or 'trough' amplitude and a maximum or 'crest' amplitude. The coupling of the first and second amplifiers through a quarter-wave line allows the signal current of the second amplifier to modulate the effective load impedance seen by the first amplifier to provide efficient amplifier coupling.

RF power amplifier stability

Abstract: A high efficiency stable RF power amplifier with frequency tuning capability is disclosed. The present invention includes a novel circuit configuration which allows the drain or collector terminal of the power transistor to be at ground potential eliminating the need for an electrical insulator between the transistor and the heatsink. In an alternative embodiment, the source or emitter terminal of the power transistor is allowed to be at ground potential. In either case, the amplifier is operated in a switched mode to provide high efficiency amplification at a predetermined frequency band. Additionally, despite the switched mode operation, the amplifier is stable because properly controlled impedances are provided for baseband, sub-harmonic and harmonic frequencies.

Radio frequency transmitting circuit

Abstract: An object of the present invention is to allow the miniaturization of a mobile communication equipment and the reduction of consumption power, and to improve the electrical characteristics of a final stage amplifier. An inputted RF signal is amplified to a specified transmission output by a final stage amplifier, the output power and a reflected wave generated by mismatching between an output impedance of the final stage amplifier and a load impedance connected to an output side of the final stage amplifier are detected by a directional coupler. Two switches are selectively switched in a time division manner, a DC voltage corresponding to the reflected wave is selected, a comparator compares a threshold voltage with the DC voltage, a switch is switched by an output of the comparator outputted in accordance with the comparison, and gate voltages are selectively applied to the final stage amplifier.

FET-OR circuit and power supply circuit using the same

Abstract: An OR circuit allowing one stable output voltage from a plurality of input voltages is disclosed. A first FET is connected between a corresponding input terminal and an output terminal in such a manner that an inherent diode of the FET is connected in a forward direction. A second FET is connected between a corresponding input terminal and the output terminal in the same manner as the first FET. Each of the input voltages is compared with the output voltage. The conduction/non-conduction states of each of the first and second FETs are independently controlled depending on the comparison result.

Low-power, low-noise dual gain amplifier topology and method

Abstract: In a low-heightened power, low-heightened noise dual gain amplifier, first and second, transistors have their emitter-collector circuits connected in series between the ground and a bus voltage. A radio frequency input terminal is coupled to the bases of both transistors. The first transistor is connected across the ground and an output terminal and operated in the common emitter mode. The first transistor operates as a high gain amplifier. A second transistor is connected across the output terminal and a bus voltage. First and second switching transistors switch first and second biasing sources to render first and second amplifier transistors conducted for operation in the high gain or low gain mode. Additionally, a third switching transistor is ac coupled across the input terminals of the first and second amplifier transistors. The third switching transistor is biased along with the first switching transistor for selectively coupling the RF input to the high gain or low gain amplifying transistor.

Microcontroller having an on-chip high gain amplifier

Abstract: A microcontroller includes a wide band, high gain amplifier on-chip capable of driving a 32 ohm speaker. The amplifier is controllable by the microcontroller processor to either enable or disable the amplifier and switch between multiple modes of power. In one embodiment, one or more such amplifiers are situated anywhere on the integrated circuit die including at the corners of the die.

Sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuit

Abstract: An improved sense amplifier ad method for sensing signals in a silicon-on-insulator (SOI) integrated circuit improve the performance of semiconductor memories and other circuits implemented in SOI technology. The bodies of amplifier transistors within the sense amplifier and bodies of input transistors to the sense amplifier are coupled to corresponding input signals, eliminating the history dependance that would result from unconnected bodies, while achieving faster switching times due to a dynamically produced difference in threshold voltage of the input transistors and amplifier transistors. The switching time is improved over circuits using input transistors and amplifier transistors having statically biased bodies.

A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier

Abstract: A 2.4-GHz, 2.2-W, 2-V fully integrated circular geometry power amplifier with 50 /spl Omega/ input and output matching is fabricated using 2.5 V, 0.35 /spl mu/m CMOS transistors. It can also produce 450 mW using a 1 V supply. Harmonic suppression is 64 dB or better. An on-chip circular-geometry active-transformer is used to combine several push-pull low-voltage amplifiers efficiently to produce a larger output power while maintaining a 50 /spl Omega/ match. This new on-chip power combining and impedance matching method uses virtual AC grounds and magnetic couplings extensively to eliminate the need for any offchip component such as wirebonds. It also desensitizes the operation of the amplifier to the inductance of bonding wires and makes the design more reproducible. This new topology makes possible a fully-integrated 2.2 W, 2.4 GHz, low voltage CMOS power amplifier for the first time.

Ultra wideband transmitter with gated push-pull RF amplifier

Abstract: A method and an apparatus that reduce power consumption in an ultra wideband (UWB) transmitter that includes a push-pull RF amplifier and a switch that powers up or powers down the amplifier between UWB pulses The gated push-pull amplifier amplifies the UWB pulses, including spurious signal energy appearing at the detector input, by splitting the signal with a 180-degree phase splitter, amplifying the split signals with substantially identical amplifiers, and combining the amplifier outputs with a 180-degree combiner The 180-degree combiner essentially cancels common-mode spurious signals typically generated by the UWB amplifier during power-down and power-up

Magneto-resistive memory having sense amplifier with offset control

Abstract: A magneto-resistive memory is disclosed that includes a high-speed sense amplifier that can reliably operate at low signal levels. The sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.

A nonlinear capacitance cancellation technique and its application to a CMOS class AB power amplifier

Abstract: A nonlinear cancellation technique is developed specifically for MOS class AB power amplifiers. This technique utilizes a PMOS transistor at the amplifier input to cancel the variation of the input capacitance, thus improving the overall amplifier linearity. A monolithic CMOS RF power amplifier with this technique is designed and fabricated in a standard 0.6 /spl mu/m CMOS technology. The prototype single-stage amplifier has a measured drain efficiency of 40% and a power gain of 7 dB at 1.9 GHz. Linearity measurements show that the new amplifier has over 10 dB of IM/sub 3/ improvement and 6 dB of ACPR improvement compared with the traditional NMOS class AB power amplifier.

Low power low noise amplifier

Abstract: A low power low noise amplifier achieves a high power gain without increasing power consumption by sharing the bias current. The amplifier is composed of a cascade structure which consists of a parallel connected common source transistor and common gate transistor connected to a common source transistor, an inverter type structure connected to the common source transistor, and structure improving the third-order intermodulation component using the parallel connected common source transistor and common gate transistor.

Broadband GaN HEMT push-pull microwave power amplifier

Abstract: We report a broadband, linear, push-pull amplifier that utilizes GaN-based HEMTs grown on SiC substrates. The high power density capabilities of these devices can be enhanced by the high efficiency achievable with push-pull operation. Good amplifier performance is facilitated by use of a new low-loss balun that is implemented with three symmetric coupled lines and which showed insertion loss of less than 0.5 dB per balun. The bias was injected through the baluns, thereby simplifying the amplifier design and reducing loss associated with dc decoupling capacitors. Using two 1.5 mm HEMTs with 0.35-/spl mu/m gate length, a push-pull amplifier produced a small-signal gain of 8 dB at 5 GH2, a 3 dB bandwidth of 3.5-10.5 GHz, and a PAE of 25%.

Power amplifier using upstream signal information

Abstract: A power amplifier system uses upstream signal information of a signal to be amplified by an amplifier to control the operation of the amplifier, thereby enabling the amplifier to operate more efficiently overall. The power amplifier system can reconfigure the amplifier based on upstream signal information, such as the measured peak power, the measured average power, the number of users, the type of carriers (CDMA, TDMA, FDMA), the number of carriers and/or the average power per carrier. For example, based on upstream signal information for the signal to be amplified, processing circuitry can reconfigure the power amplifier architecture to adjust the peak power handling capability of the amplifier. By reducing the peak power handling capability of the amplifier, the long-term efficiency of the amplifier can be improved. The power amplifier system can adjust at least one operating characteristic of the amplifier while maintaining the configuration of the amplifier, for example by adjusting the bias voltage(s) to the amplifier based on upstream signal configuration information.

High-frequency amplifier and high-frequency multistage amplifier

Abstract: A T-type circuit having series resistors and a parallel resistor is arranged on the outside of an amplifier, a signal is amplified in the amplifier while stabilizing the signal by using the T-type circuit functioning as a stabilizing circuit, and the amplified signal is output. In this case, values of the series resistors and the parallel resistor of the T-type circuit are determined so as to set an output load impedance obtained by seeing the output side of the high-frequency amplifier from the amplifier to a value near to or slightly lower than a value of the conjugate complex impedance of an output impedance of the amplifier. Therefore, the output signal having a high output electric power and a low distortion can be obtained in the high-frequency amplifier while keeping a gain and a noise characteristic of the high-frequency amplifier.

Stepped gain controlled RF driver amplifier in CMOS

Abstract: A variable gain amplifier has at least two branches connected in parallel to drive a common output load Each branch includes at least two FETs in a cascode configuration A first FET in each branch is arranged to receive an input signal and to amplify the signal in a common source configuration; the second FET is arranged in a common gate configuration with its source receiving the output current of the first FET The gate of the second FET is coupled to a corresponding gain control input so that the second FET is enabled when the gate receives an enabling gain control signal and disabled otherwise Preferably the first and second FETs in each branch are biased in a saturation region of operation when the second FET is enabled by the gain control input This maintains a low distortion figure throughout the dynamic range of the gain control Preferably, the invention also includes an active fixed gain power amplification stage for coupling the output to a power amplifier

Power switch for battery protection

Abstract: A new battery charging, discharging, and protection circuit is achieved. The circuit comprises, first, a FET switch having gate, source, drain, and bulk. The FET switch may comprise either a NMOS device or a PMOS device. The source is coupled to a load terminal, and the drain is coupled to a battery terminal. Second, a means of controlling the FET switch gate and the bulk is included. The FET switch gate voltage determines the OFF and ON state of said FET switch. The bulk is switchably coupled between the battery terminal and the load terminal. A cascaded version is disclosed.

A low voltage, rail-to-rail, class AB CMOS amplifier with high drive and low output impedance characteristics

Abstract: This paper describes a CMOS rail-to-rail class AB operational amplifier designed to have extremely low output impedance and large current-drive capability. The amplifier uses an innovative output stage, having both source follower and common source stages working simultaneously throughout the output common-mode range. The source follower ensures low output impedance, which enables it to drive relatively large load capacitors, while the common-source gain stage provides high current drive. Furthermore, the circuit is fully functional with supplies as low as 1.5 V. The amplifier is capable of driving a maximum output current of /spl plusmn/7 mA with only 140 /spl mu/A of total quiescent current, making it power efficient, and thus appropriate for low voltage battery-powered applications.

Optical amplifier control system

Abstract: An optical amplifier control system provides real-time control of an optical amplifier in response to an analog signal having a large dynamic range. The optical amplifier control system uses a non-linear analog-to-digital converter, such as a logarithmic-scale analog-to-digital converter to achieve low relative quantization error. The amplifier control system may also use multiple analog-to-digital converters.