Showing papers on "Field-effect transistor published in 1974"

Design of ion-implanted MOSFET's with very small physical dimensions

Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

High-speed integrated logic with GaAs MESFET's

Abstract: The feasibility of using GaAs metal-semiconductor field-effect transistors (GaAs MESFET's) in fast switching and high-speed digital integrated circuit applications is demonstrated. GaAs MESFET's with 1-/spl mu/m gate length are shown to have a current-gain-bandwidth product f/SUB T/ equal to 15 GHz. These devices exhibit a 15 ps internal delay in a large-signal switching test. A simple logic circuit consisting of MESFET's and Schottky diodes was monolithically integrated on a semiinsulating GaAs substrate. This logic circuit exhibits a propagation delay of 60 ps with no output load, and 105 ps when its output is loaded by three similar logic gates. A useful bandwidth of approximately 3 GHz is observed.

Famos—A new semiconductor charge storage device

Abstract: A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p -channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p - n junction to yield reproducible charging characteristics with long term storage retention.

Insulated-gate thin film transistor with low leakage current

Abstract: An insulated-gate thin film transistor is provided with low leakage drain current. A second semiconductor layer makes contact with the source electrode and the semiconductor layer forming the channel of the transistor at least between the source and drain electrodes. The second semiconductor layer is of opposite type conductivity from the channel semiconductor layer and preferably forms a PN heterojunction with the channel semiconductor layer. Alternatively, a metal layer may be used in place of the second semiconductor to form a Schottky-barrier junction with the channel semiconductor layer instead of a PN junction. Preferably, the channel semiconductor layer and the second semiconductor layer or the metal layer are sequentially evaporation deposited through the same deposition mask onto a substrate from evaporant sources spaced substantially different distances from the substrate so that the sequential layers are deposited on first and second overlapping areas of the substrate.

Deep depletion insulated gate field effect transistors

Abstract: A deep depletion insulated gate field effect transistor is made in a silicon layer on a sapphire substrate, so that its threshold voltage is relatively independent of the thickness of the silicon layer. The silicon layer has two parts, namely, a lower part adjacent to the sapphire substrate which is relatively lightly doped, and an upper part, preferably formed by ion implantation, having a doping concentration on the order of about 2 × 10 15 atoms/cm 3 .

Level shifter circuit

Abstract: An improved TTL to MOS voltage level shifter circuit utilizes a totem pole output stage consisting of a pull-up junction transistor and a pull-down saturation junction transistor, an intermediate stage consisting essentially of a saturation junction transistor, an input stage consisting essentially of a diode and a saturation junction transistor, and current spike inhibit circuitry which consists essentially of a saturation junction transistor connected between the input stage and the base of the pull-down transistor. The current spike inhibit transistor, which turns on with the pull-down transistor, has a greater turnoff time than the pull-down transistor and consequently provides a relativley low impedance discharge path connected to the base of the pull-down transistor which allows the pull-down transistor to turn off before the pull-up transistor turns on. This helps insure against output current spikes that occur if the pull-up and pull-down transistors conduct simultaneously.

Semiconductor device and method of manufacturing the device

Abstract: A semiconductor device having at least an insulated gate field effect transistor. According to the invention, the device comprises a first semiconductor region of a first conductivity type, an inset insulating pattern in a surface of said semiconductor region, a second region of the second conductivity type surrounded by said pattern, and source and drain zones of the first conductivity type which adjoin the insulating pattern. Said field effect transistor is preferably combined with a complementary field effect transistor provided beside it in the first region. The invention also comprises a very advantageous method of manufacturing said structure in which the insulating pattern and the gate electrodes serve as masks.

Interconnection in multi element planar structures

Abstract: A field effect transistor wherein at least one of source, drain and gate electrodes on a semiconductor substrate is a multi electrode array above a common conductor on the bottom of the substrate. A conductive connection between electrodes of the array and the common conductor is completed through holes in the substrate.

Protection circuit for insulated-gate field-effect transistors

Abstract: Two current-carrying paths are connected in parallel between a signal input terminal and an internal node to which are connected the gate electrodes of insulated-gate field-effect transistors to be protected. One path includes the conduction path of a first transistor of one conductivity type connected in series with a first diode poled in a direction to charge the internal node and the other path includes the conduction path of a second transistor of second conductivity type in series with a second diode poled in a direction to discharge the internal node. The control electrodes of the first and second transistors are connected to points of operating potential rendering the first transistor conductive in the source follower mode for input signals of one polarity and rendering the second transistor conductive in the source follower mode for input signals of opposite polarity.

LSI chip compensator for process parameter variations

Abstract: An on chip field effect transistor circuit is disclosed for electrically compensating for variations in process parameters which have occurred during the course of fabrication of the integrated circuit chip as well as variations in environmental parameters such as supply voltages and temperature. The compensation is performed by utilizing three field effect transistor devices on the integrated semiconductor chip as a sensor to detect variations in the characteristics of the devices due to deviations in the process parameters during fabrication thereof. The sensing field effect transistors operate in a circuit to adjust the gate potential of FET load devices in those functional circuits on the integrated circuit chip whose sensitivity to the variations in the process parameters is critical to the operation of the circuit as a whole.

Process for the production of a pair of complementary field effect transistors

Abstract: A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which first and second gate electrodes are formed for the two transistors. A masking oxide layer is applied to the exposed surface regions of the gate insulating layer and the gate electrodes. An opening is etched into the masking layer and gate insulator layer lying adjacent each gate electrode. Charge carriers of first and second types are diffused through the respective openings into the region of the semiconductor layer lying below to dope the same. This doping extends partially into the semiconductor region lying beneath a portion of the respective gate electrodes. All parts of the gate insulator layer except those parts lying beneath the gate electrodes are removed. Charge carriers of the second and first type are diffused into the semiconductor layer on opposite sides of the first and second gate electrodes, respectively, while leaving a portion of the first and second doped regions unchanged beneath the first and second gate electrodes. The doped regions of the semiconductor layer on opposite sides of the first and second gate electrodes provide the source and drain regions of the first and second field effect transistors, respectively.

Method of making an insulated gate field effect transistor

Abstract: An improved insulated gate field effect transistor is achieved by using a material such as silicon nitride as an ion implantation and oxidation mask overlying a channel region, forming source and drain regions or extensions thereof by implanting ions of a conductivity modifier into a semiconductor substrate, and subjecting the implanted ions to a drive-in diffusion whereby the conductivity modifier ions are redistributed. The ion implantation allows greater control over the amount of conductivity modifier implanted in the lightly doped source and drain regions, the more uniform distribution of conductivity modifier increases the source-drain breakdown voltage, while the use of the silicon nitride mask provides simultaneously for general alignment of the channel region with the effective gate length.

Oxide isolated integrated injection logic with selective guard ring

Abstract: A process for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors incorporates the steps of growing a doped epitaxial layer of single-crystal silicon on a silicon substrate, applying a first insulation material in a selected pattern over the epitaxial layer to define oxide-isolation regions and device regions, etching grooves in the areas in which oxide-isolation regions will be formed, applying a self-aligned base insulation material over those portions of the interface between the first insulation material and the grooves which bound the region between the base of any vertical bipolar transistor to be formed and the emitter of any lateral bipolar transistor to be formed, applying an impurity of a conductivity type opposite to the conductivity type of the epitaxial layer to those groove areas not covered by the self-aligned base insulation material, the impurity serving to prevent emitter-to-collector inversion along the wall of the base of any vertical bipolar transistor without shorting the emitter and collector of any lateral bipolar transistor, forming oxide-isolation regions in the grooves and forming the vertical bipolar transistors and the lateral bipolar transistors in the device regions. The process of the present invention will produce discrete lateral bipolar transistors, discrete vertical bipolar transistors capable of operation in the conventional mode or in the inverse mode, or a composite structure which merges both a vertical bipolar transistor and a lateral bipolar transistor together on the same silicon island to form an injection-logic gate in which the base of the vertical bipolar transistor serves as the collector of the lateral bipolar transistor, the vertical transistor being operated in the inverse mode.

D.C. power source with temperature compensation

Abstract: An improved D. C. power source whose output voltage is independent of changes in temperature is disclosed. Compensation for changes in temperature is established by three features. For a change of the voltage drop in the forward direction between the base and the emitter of a transistor, a plurality of diodes provided in a bias circuit in the transistor are utilizied; for a change of the current amplification factor β of a transistor, an additional transistor is attached to the transistor, and; for a change of the value of an emitter resistor connected between the emitter of the transistor and the ground, an external stable resistor is utilized. The D. C. power source of the present invention is, in particular, useful for an integrated circuit.

Differential charge transfer sense amplifier

Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

Enhancement mode, Schottky-barrier gate gallium arsenide field effect transistor

Abstract: Disclosed is a new process for fabricating field effect transistors, and particularly enhancement mode and depletion mode Schottky-gate field effect transistors. The process includes the steps of forming a thin layer of gate metalization over the FET channel region, and this gate metalization is then exposed to the bombardment of protons with sufficiently high energy to penetrate through the gate metalization layer and enter the channel region of the FET and there produce deep level energy traps in the channel region. These traps serve to tie up carriers and create donor and acceptor vacancy complexes in the FET channel. This step has the effect of raising the resistivity of the FET channel and is used to make the FET device non-conducting with zero voltage on the gate metalization, i.e., an enhancement mode device.

Highly sensitive gate-controlled pnpn switching circuit

Abstract: A PNPN switch having substantially a fourlayer structure has at least its first, third and fourth layers, which have respectively P,P and N conductivity types, provided respectively with a first, third and fourth electrodes. The source and the drain of a field effect transistor is connected with the third and fourth electrodes, respectively. The third electrode is further connected with one end of a voltage drop element while the other end of the voltage drop element is connected with the gate of the field effect transistor. The gate of the field effect transistor and the other end of the voltage drop element, connected together, serve as a gate trigger terminal of a highly sensitive gate-controlled PNPN switching circuit.

Radiation induced charge trapping at the silicon sapphire substrate interface

Abstract: The radiation induced charge trapping at the silicon sapphire interface and its effect on MIS/SOS device performance has been experimentally determined for a total ionizing dose up to 108 rads (Si). These effects were determined by measuring the electrical characteristics of three types of device structures fabricated in SOS material: MIS devices with hardened and unhardened gate insulators, JFET's and diodes. The main emphasis is on the use of novel JFET structures for characterizing the SOS interface by modulating the gate depletion region against the sapphire substrate. Micrographs are also presented which show radiation induced changes in the staining characteristics of angle lapped and stained sections of the SOS interface. The experimental results indicate that positive charge is trapped in the sapphire substrate near the silicon-sapphire interface due to the total ionizing radiation. A model of the radiation induced charge trapping at the silicon sapphire interface is proposed.

Method of manufacturing a semiconductor device having closely spaced electrodes by perpendicular projection

Abstract: A Shottky barrier gate field effect transistor is produced by etching a first conductive film formed on a semiconductor crystal surface using a mask to leave a first conductive film area smaller than the area of the mask and projecting a second conductive material on to the surface perpendicularly thereof. The second conductive film areas thus formed and the first conductive film area serve as the source and drain electrodes and the gate electrodes, respectively.

D. C. Stable semiconductor memory cell

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Schottky barrier infrared detector arrays with charge coupled device readout

Abstract: Schottky barrier detector arrays for detecting the infrared portion of the spectrum connected through enhancement mode field effect transistors to a charge coupled device for read out. The system utilizes a voltage to charge conversion to provide an infrared camera device vidicon.

LSI array using field effect transistors of different conductivity type

Abstract: A large scale integrated (LSI) array of standard cells arranged in rows and columns adapted to receive different metallization patterns for producing custom circuits. Disposed in one half of each cell is a first power contact and contacts for the sources, drains and gates of field effect transistors of one conductivity type. Disposed in the other half of each cell is a second power contact and contacts for the sources, drains and gates of field effect transistors of complementary conductivity type. The pattern formed by the contacts in one half of a cell is the mirror image of the pattern formed by the contacts in the other half of the cell. The symmetry of the components of each cell is such that the metal interconnection pattern of a cell or a combination of cells for producing a given logic function may be inverted about the horizontal or the vertical plane of symmetry of the cell for producing a logic function relates to said given logic function.

Elimination of SCR structure

Abstract: A complementary field effect transistor structure which eliminates the problems caused by parasitic currents between devices. The currents are contained within parasitic bipolar devices formed between the various regions of the FETs. A portion of the collector current of the parasitic bipolar devices is drained away so that the loop gain is less than one. This is achieved by placing guard regions of conductivity type which are the same as the channel type of the transistors adjacent said regions. The guard region is preferably in the form of a continuous ring around its associated FET.

wo-dimensional finite element simulation of semiconductor devices

Abstract: Semiconductor-device modelling in two dimensions by the finite-element method is described. Results of application to a GaAs m.e.s.f.e.t. are given. Negative differential drain conductance is observed.

Field effect transistor devices and methods of making same

Abstract: Relates to JFET field effect transistor devices formed in a substrate including a first and third layers of low resistivity adjacent opposed major surfaces of the substrate and a second intermediate layer of high resistivity. The third layer is provided with an opening exposing the second layer. A mesa or projection is epitaxially grown in the opening from the second and third layers. By proper provision of the conductivity type in the three layers and the projection, the projection may constitute either the source or gate region, and correspondingly the third layer would constitute the gate or source region. The first layer constitutes the drain region.

IGFET on an insulating substrate

Abstract: The breakdown voltage of a novel insulated gate field effect transistor (IGFET), comprising silicon on sapphire (SOS), is substantially doubled by a novel structure wherein a dielectric layer, formed over a channel region of the IGFET, also extends continuously over the surface of the sapphire on opposite sides of the channel region. A polysilicon gate electrode is disposed over the dielectric layer, the gate electrode extending beyond the channel region and being separated from the sapphire substrate by the dielectric layer. The novel method of making the IGFET comprises providing an island of epitaxially deposited doped silicon on the sapphire substrate, and dielectric layer extending continuously over both the island and over portions of the substrate on opposite sides of the island.

Process for fabricating insulated gate field effect transistor structure

Abstract: An improved and simplified process for fabricating a complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate wherein the source/drain regions of at least one of the complementary p-channel or n-channel field effect devices are formed by the steps of introducing an impurity of one conductivity type and then introducing an impurity of the opposite conductivity type, one of the impurities having a relatively greater concentration than the other so that the one impurity counterdopes the other and the source/drain regions are characterized by the conductivity type of the one impurity.

Superconducting tunnel junction bolometers

Abstract: Two new types of superconducting infrared bolometer are described. In one, the temperature dependent Josephson current in an SNS junction is measured with a SQUID galvanometer. In the other, the temperature-dependent quasiparticle tunneling current in an SIN junction is measured with a conventional fet amplifier. Either type of junction is deposited on a low heat capacity sapphire substrate covered on the reverse side with a thin Bi film to absorb infrared radiation. The best performance achieved thus far is for the SNS bolometer which has an electrical NEP ~ 5 x 10 -15 W/√Hz and D* ~ 1014 cm. W-1. Hz1/2. Some improvement in these values is anticipated.