Showing papers on "Filter capacitor published in 2013"

Voltage Balancing and Fluctuation-Suppression Methods of Floating Capacitors in a New Modular Multilevel Converter

Abstract: Modular multilevel converter (MMC) is a newly emerging multilevel topology for high-voltage applications during recent years. In this paper, a new MMC is proposed, and the structure and operating principle are analyzed. Owing to the cascaded basic cells without multiwinding transformer, the voltage balancing of floating capacitors must be considered. However, the voltage fluctuation also exists, and theoretical analysis indicates that the amplitude is inversely proportional to the fundamental frequency. This paper has proposed a voltage-fluctuation-suppression method which can reduce the amplitude of the voltage fluctuation in low-frequency region. It can also be used in motor driving with pump/blowerlike load at low frequency and improve the start-up performance significantly. A low-power three-phase five-level prototype is designed and built up to demonstrate the validity of this method.

Active Power Decoupling for High-Power Single-Phase PWM Rectifiers

Abstract: Single-phase pulsewidth modulation rectifiers suffer from ripple power pulsating at twice the line frequency. The ripple power is usually filtered by a bulky capacitor bank or an LC branch, resulting in lower power density. The alternative way is active power decoupling, which uses an active circuit to direct the pulsating power into another energy-storage component. The main dc-link filter capacitor can, therefore, be reduced substantially. This paper proposed a new scheme of active power decoupling. The circuit consists of a third leg, an energy-storage capacitor and a smoothing inductor. The topology combined the advantages of high energy-storage efficiency and low requirement on control bandwidth. Both the pulsating power from the ac source and the reactive power of the smoothing inductors are taken into consideration when deriving the power decoupling scheme. The active power filter's (APF) capacitor voltage control system consists of inner loop pole-placement control and outer loop proportional-resonant control. To enhance the steady-state performance, the capacitor voltage reference is modified in a closed-loop manner. Simulation and experimental results show that the proposed APF scheme has good power decoupling performance and is more suited for high-power applications where switching frequency is limited.

Novel High Step-Up DC–DC Converter for Distributed Generation System

Abstract: In this paper, a novel high step-up dc-dc converter for distributed generation systems is proposed. The concept is to utilize two capacitors and one coupled inductor. The two capacitors are charged in parallel during the switch-off period and are discharged in series during the switch-on period by the energy stored in the coupled inductor to achieve a high step-up voltage gain. In addition, the leakage-inductor energy of the coupled inductor is recycled with a passive clamp circuit. Thus, the voltage stress on the main switch is reduced. The switch with low resistance RDS(ON) can be adopted to reduce the conduction loss. In addition, the reverse-recovery problem of the diodes is alleviated, and thus, the efficiency can be further improved. The operating principle and steady-state analyses are discussed in detail. Finally, a prototype circuit with 24-V input voltage, 400-V output voltage, and 200-W output power is implemented in the laboratory to verify the performance of the proposed converter.

High Power Factor AC–DC LED Driver With Film Capacitors

Abstract: In this paper, a new method is proposed to eliminate electrolytic capacitors in a two-stage ac-dc light-emitting diode (LED) driver. DC-biased sinusoidal or square-wave LED driving-current can help to reduce the power imbalance between ac input and dc output. In doing so, film capacitors can be adopted to improve LED driver's lifetime. The relationship between the peak-to-average ratio of the pulsating current in LEDs and the storage capacitance according to given storage capacitance is derived. Using the proposed “zero-low-level square-wave driving current” scheme, the storage capacitance in the LED driver can be reduced to 52.7% comparing with that in the driver using constant dc driving current. The input power factor is almost unity, which complies with lighting equipment standards such as IEC-1000-3-2 for Class C equipments. The voltage across the storage capacitors is analyzed and verified during the whole pulse width modulation dimming range. For the ease of dimming and implementation, a 50 W LED driver with zero-low-level square-wave driving current is built and the experimental results are presented to verify the proposed methods.

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

Abstract: Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.

Stacked Switched Capacitor Energy Buffer Architecture

Abstract: Electrolytic capacitors are often used for energy buffering applications, including buffering between single-phase ac and dc. While these capacitors have high energy density compared to film and ceramic capacitors, their life is limited. This paper presents a stacked switched capacitor (SSC) energy buffer architecture and some of its topological embodiments, which when used with longer life film capacitors overcome this limitation while achieving effective energy densities comparable to electrolytic capacitors. The architectural approach is introduced along with design and control techniques. A prototype SSC energy buffer using film capacitors, designed for a 320 V dc bus and able to support a 135 W load, has been built and tested with a power factor correction circuit. It is shown that the SSC energy buffer can successfully replace limited-life electrolytic capacitors with much longer life film capacitors, while maintaining volume and efficiency at a comparable level.

A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices

Abstract: Wireless power transfer has a broad range of applications ranging from mobile phone chargers to biomedical implants. For cochlear implants [1] and retinal prostheses [2], having a miniaturized form factor and being battery-less are highly desirable. Such devices require real-time power transfer in the range of 10 to 100mW [3], and as human tissue specific absorption rate (SAR) increases with frequency, inductively-coupled power links that operate at 13.56MHz or lower in ISM bands are commonly used, as shown in Fig. 4.2.1. However, lower transmission frequency means larger matching and filtering capacitors that are bulky. In addition, the received AC input amplitude VAC,Peak would fluctuate due to changes in distance and orientation between the coupling coils. Hence, comparator- controlled power switches (active diodes) are used to replace diodes so that the rectifier could work at a lower VAC,Peak and still achieve a high voltage conversion ratio (VCR) and power conversion efficiency (PCE) [4]. In this research, we present the first fully integrated 1X/2X active rectifier in the 30mW range with all capacitors fabricated on-chip, also shown in Fig. 4.2.1. This is made possible by a switching arrangement that avoids connecting the output capacitors in series in the 2X mode. Reverse current is reduced for VAC,Peak that ranges from 1.25 to 4V by a bias current that is quasi-inversely proportional to the output DC voltage, as explained later; and efficiency is carefully measured by the insertion of a sensing resistor plus an additional capacitor to reduce distortion.

A frequency-domain study on the effect of DC-link decoupling capacitors

Abstract: DC-link decoupling capacitors are generally placed near the power switches in the converter to minimize the parasitic ringing and voltage overshoot on the devices. In this paper, the influence of decoupling capacitors on the turn-off parasitic ringing of power MOSFETs is studied in the frequency domain based on a small-signal modeling approach. This new angle helps explain the effect of these capacitors in a simpler and more straightforward way compared to the traditional time-domain analysis, and provides a deeper insight into the problem. A rule of thumb about the selection of effective decoupling capacitance value can also be derived from this study.

Single- and Three-Phase PHEV Onboard Battery Charger Using Small Link Capacitor

Abstract: This paper suggests a new onboard charger for plug-in hybrid electric vehicle. It has a cascade structure of a high-frequency resonant converter with a constant switching frequency for electrical isolation and discontinuous-conduction-mode buck-boost converter for charge control and harmonic regulation of input current under universal line input. This structure uses small link capacitors so that high-voltage electrolytic capacitors that are not preferable to be used in automotive applications due to its short lifetime can be removed. The feasibility of the proposed charger has been verified with single-phase and three-phase prototypes.

Sensorless Control of CSC-Fed IPM Machine for Zero- and Low-Speed Operations Using Pulsating HFI Method

Abstract: In this paper, a sensorless method for low- and zero-speed operations is proposed for a high-power medium-voltage pulsewidth-modulated current-source-converter-fed interior-permanent-magnet motor drive system. The proposed method is based on the injection of a high frequency (HF) pulsating sinusoidal signal in the estimated synchronous reference frame of the drive's field-oriented control (FOC) scheme. The conventional FOC control scheme, low switching frequency, dc-link inductor, and the inverter output three-phase filter capacitor of the medium-voltage high-power current-source drive present some challenges in the generation and design of the HF-injection signal. To overcome these challenges, the FOC scheme is modified by introducing a modulation index control with suitable dc-link current compensation to enhance the dynamic response of the injected signal and prevent any clamp in the injected signal. In addition, a multisampling-space-vector-modulation method is proposed to prevent the distortion in the HF signal due to a low switching frequency to injected signal ratio. A detailed study and analysis regarding the influence of low switching frequency, output filter capacitor, and magnetic saturation in the injection method is carried out to determine the visible HF range of the injected signal. It is found that, by using the proposed FOC scheme and multisampling modulation scheme and by the proper design of the HF signal, an accurate rotor flux angle can be estimated for sensorless zero-/low-speed operations. Experimental results are provided to verify the proposed control method.

Observer based active damping of LCL resonance in grid connected voltage source converters

Abstract: Voltage source converters (VSC) with LCL filters are attractive in grid connected applications because they greatly reduce pollution of the utility voltage due to switching harmonics. However, LCL network has very low impedance at frequencies close to resonance and therefore even small voltage magnitudes at those frequencies can excite currents of large magnitudes or even cause instability. In this paper novel current controller structure is proposed that uses Luenberger observer as a sensor replacement and state predictor to predict filter capacitor current which is passed through virtual resistor to create damping effect. Predicted filter capacitor through virtual resistor is inner fast loop, while outer loop with appropriate feedforward terms ensures fast command tracking and zero steady-state error. The use of the observer alleviates the impact of sampling delay which greatly improves active damping capability and eliminates the need for additional sensors. This paper with simulation and experimental results demonstrates true active damping and the effectiveness of the virtual resistance in actively stiffening input impedance of AFE drive at frequencies close to resonance.

A Three-Level Converter With Reduced Filter Size Using Two Transformers and Flying Capacitors

Abstract: This paper proposes a pulse-width modulation three-level converter with reduced filter size using two transformers. The proposed converter has many advantages. All switches sustain only the half of the input voltage and since the secondary rectified voltage is a three-level waveform, the output filter inductor can be reduced. Also, because of the power sharing of transformer and reduced output inductor, high efficiency can be obtained. The operational principle, analysis, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 600 W, 500-600 V input, and 60 V output.

Design and Research on the LCL Filter in Three-Phase PV Grid-Connected Inverters

Abstract: With the energy crisis and environment revolution are becoming more and more serious, renewable power generation system is drawing more and more attention. We vigorously developed clean energy such as wind, and solar power. The control technology of grid-connected inverter is the key technology in renewable power generation. In the grid-connected inverter, the all-controlled power electronic devices IGBT and GTO are be used, which is modulated by the high frequency PWM. As the result, the du/dt and di/dt are ever large. Due to the presence of some vagrant parameters, the current included high order harmonic flow into the power grid, which made the harmonic pollution. The most common filter is L in the grid-connected inverter. In order to decrease current ripple, the inductance have to be increased. As a result, the volume and weight of the filter increased. Although the structure and the parameter of the LC filter are easy, the filtering effect is not good because of the uncertainty of network impedance. LCL filter had an inherently high cut-off frequency and strong penetrating ability in low frequency. So LCL filter has come into wide use in the inverter. What is the most difficult is that how to select the parameter and control resonance. In this paper, with the three-phase PV grid-connected inverters topology, firstly analyze the inductance, the ration of two inductances, selecting the filter capacitor and resonance resistance. Based on these theories, a LCL filter is designed. The simulation result proved that the LCL filter achieve the best performance, and indicated the impacts on the stability and filtering property from the parallel resistor or

A Common-Mode Choke Using Toroid-EQ Mixed Structure

Abstract: Electromagnetic interference (EMI) filters are main solutions to suppress the conducted emissions from static power converters. For some years, integration techniques for EMI filters have been widely investigated to realize more compact systems. In this letter, a common-mode (CM) choke with toroid-EQ mixed structure is presented. This structure is constituted of a toroidal CM choke embedded into an EQ core. The proposed toroid-EQ CM choke presents threefold advantages. First, it effectively increases the leakage inductance of the toroidal CM choke and hence increases the differential-mode inductance. Second, it reduces the parasitic coupling between the choke and the filter capacitors. Finally, the component can be easily fabricated with low cost. Experimental verifications have been carried out to validate the effectiveness of the proposed toroid-EQ CM choke.

Stacked switched capacitor energy buffer circuit

Abstract: A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range.

Reliability-oriented design and analysis of input capacitors in single-phase transformer-less photovoltaic inverters

Abstract: While 99% efficiency has been reported, the target of 20 years of service time imposes new challenge to cost-effective solutions for grid-connected photovoltaic (PV) inverters. Aluminum electrolytic capacitors are the weak-link in terms of reliability and lifetime in single-phase PV systems. A reliability-oriented design guideline is proposed in this paper for the input capacitors in single-phase transformer-less PV inverters. The guideline ensures that the service time requirement is to be accomplished under different power levels and ambient temperature profiles. The theoretical analysis has been demonstrated by a 1 kW single-phase PV inverter.

Three-phase five-level active-neutral-point-clamped converters for medium voltage applications

Abstract: In this paper various five-level active-neutral-point-clamped converters (ANPCCs) are proposed. These, as for the conventional ANPCC structure, are constructed with a combination of neutral-point-clamped and floating capacitor converter technologies. Depending on the new circuit arrangement, better total semiconductor conduction losses and/or the requirement of lesser active switch part count are achievable when compared to a conventional ANPCC. Additionally, a modulation scheme providing well regulated, balanced and low voltage ripples across the dc-bus capacitors for the studied ANPCCs is presented. The voltage balancing across the phase capacitors is performed by selecting the multilevel converter redundant switching states, which results in different current direction across this device. The technique is implemented in a carrier-based PWM modulation scheme.

Enhanced stacked switched capacitor energy buffer circuit

Abstract: A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range.

Evaluation of DC-link decoupling using electrolytic or polypropylene film capacitors in three-phase grid-connected photovoltaic inverters

Abstract: The life expectancy and long term reliability of grid-connected three-phase photovoltaic (PV) inverters can be increased by replacing the conventional electrolytic film capacitors by metallized polypropylene film capacitors. This paper presents a detailed evaluation of a three-phase grid-connected PV inverter performance when replacing the electrolytic capacitor with a minimum value of metallized polypropylene film capacitor-one. The minimum dc bus capacitance leads to larger voltage ripples. However, such ripples were found to be within acceptable limits to run the inverter satisfactorily. Simulation results are presented for a 15-kW grid-connected inverter at nominal voltage of 700V dc and experimental results are provided for a 3.0-kW system at a nominal voltage of 400V dc, built in the laboratory.

Mismatch characterization of small metal fringe capacitors

Abstract: Even though small metal fringe capacitors are important for the realization of low-energy A/D converters, present literature is lacking experimental data on their mismatch characteristics. This paper describes a test structure and measurements results pertaining to the characterization of single-layer, lateral-field, 0.45-fF and 1.2-fF unit metal capacitors in a 32-nm SOI CMOS process. The measurement-inferred average standard deviations for these capacitances are 1.2% and 0.8%, respectively, confirming area scaling according to Pelgrom's matching law.

Predictive current control in a current source inverter operating with low switching frequency

Abstract: This paper presents a novel model predictive current control method for current source inverters (CSI) following the duality with voltage source inverters (VSI) The method is based on the discrete prediction model of the system, including the converter and output filter The model is used to predict how the system variables will behave for each switching state of the converter The predictions are evaluated using a cost function that weights the level of accomplishment of the control goals The switching state with the best performance is then generated The proposed algorithm predicts the output currents (including the output filter capacitors), ensuring sinusoidal current generation without the need for cascaded control loops, coordinate transformations, and modulation schemes found in traditional solutions In addition, low switching frequency is imposed by including a new term in the cost function Simulation results validate the proposed control scheme, with performance comparable to the traditional solutions, especially in terms of the current and voltage harmonic distortion

Methods and apparatus for active front end filter capacitor degradation detection

Abstract: Apparatus and methods are provided for detecting degradation of delta-connected filter capacitors in an active front end (AFE) power converter, in which delta circuit capacitor leg currents are calculated based on measured branch circuit currents, and filter capacitor impedance values are computed based on the calculated leg currents as well as measured line-to-line voltages and corresponding phase angles for comparison with one or more thresholds to selectively detect degradation of the filter capacitors. Further apparatus and methods are provided for detecting degradation of Y-connected filter capacitors by computation of fundamental frequency RMS impedance values as ratios of RMS capacitor voltages and RMS circuit branch currents, and comparison of the calculated RMS impedance values with one or more thresholds.

Analysis and design of a parallel-connected single active bridge DC-DC converter for high-power wind farm applications

Abstract: This paper presents a parallel-connected Single Active Bridge (SAB) dc-dc converter for high-power applications. Paralleling lower-power converters can lower the current rating of each modular converter and interleaving the outputs can significantly reduce the magnitudes of input and output current ripples without increasing switching losses or device stresses. Analysis of both the input and output current characteristics and design aspects of the transformer, the filter inductor, and the input and output filter capacitors will be presented. Considering the high maintenance cost and fault tolerant requirements, this modular converter concept is expected to be highly beneficial especially for the offshore wind farm application.

All-pMOS 50-V Charge Pumps Using Low-Voltage Capacitors

Abstract: In this paper, two high-voltage charge pumps (CPs) are introduced. In order to minimize the area of the pumping capacitors, which dominates the overall area of the CP, high-density capacitors have been utilized. Nonetheless, these high-density capacitors suffer from low breakdown voltage, which is not compatible with the targeted high-voltage application. To circumvent the breakdown limitation, a special clocking scheme is used to limit the maximum voltage across any pumping capacitor. The two CP circuits were fabricated in a 0.6- μm CMOS technology with poly0-poly1 capacitors. The output voltage of the two CPs reached 42.8 and 51 V, whereas the voltage across any capacitor did not exceed the value of the input voltage. Compared with other designs reported in the literature, the proposed CP provides the highest output voltage, which makes it more suitable for tuning MEMS devices.

Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

Abstract: In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.

Effect of Combined Output Capacitors for Stability of Buck Converters With Constant On-Time Control

Abstract: Constant on-time control has been widely used for power supply controllers in industry due to its fast transient response. However, existing stability analysis in literatures can only explain conditions with single type of output capacitor and usually recommend high equivalent series resistance ( ESR) *Co for stable operation. This paper proposes a new stability analysis for constant on-time control with combined output capacitors, which are often used in practical applications. Based on time-domain analysis for the inductor current, the output voltage, and the output capacitor currents, it is revealed that higher ESR and higher capacitance values can deteriorate the stability in many conditions with combined output capacitors. Also, a simple loop compensation solution is provided to improve stability. Simulation and experimental results demonstrate the theoretical analysis.

A submodule implementation for parallel connection of capacitors in modular multilevel converters

Abstract: The modular multilevel converter is a suitable converter topology for high-voltage high-power applications and consists of series-connected submodules. Typically, these submodules are half-bridges with dc capacitors. A voltage ripple in the submodule capacitors is inevitable due to the current flowing in the arms. The converter should therefore be controlled in such a way that the capacitor voltages are kept balanced and close to their nominal values over time. This paper presents a new submodule circuit which alleviates the balancing of the capacitor voltages. The proposed submodule circuit consists of two capacitors and eight switches, forming a three-level submodule. Ideally, the voltage and current rating of the switches can be chosen such that the combined power rating of the semiconductors is the same as for equivalent half-bridge submodules. The proposed submodule circuit provides the possibility of connecting the two capacitors in parallel when the intermediate voltage level is used. This will reduce the capacitor voltage ripple, especially at low switching frequencies and thus allow for a reduction of the size, weight, and cost of the submodule capacitors. The proposed submodule circuit is validated by both simulation results and experiments on a laboratory prototype. It is found that the parallel connection of the submodule capacitors will, in fact, significantly improve the balancing of the capacitor voltages.

Single-phase active front end rectifier system for use with three-phase variable frequency drives

Abstract: A voltage source inverter comprises a rectifier having an input for receiving single-phase AC power from an AC source and converting the AC power to DC power on a DC bus. The DC bus has first and second rails to provide a relatively fixed DC voltage. A DC bus capacitor is across the first and second rails to smooth voltage ripple. An inverter receives DC power from the DC bus and converts the DC power to AC power. An active front end circuit comprises a pair of filter capacitors in series across the first and second rails to create a midpoint. A bidirectional switch is connected between the rectifier input and the midpoint. The bidirectional switch is controlled to inject current into the midpoint of the DC bus.

Synthetic-Ripple-Based Digital Hysteretic Modulator for Point-of-Load Converters

Abstract: In the modern point-of-load (POL) applications, a number of low- and medium-power converters are used very close to the actual load. These applications require superior dynamic response and better power processing density to save space on the motherboard. Hysteretic modulators are one of the obvious choices for these applications because of their superior dynamic response with minimal number of filter capacitors. This paper presents a new carrier (synthetic ripple based)-generation-based digital hysteretic modulator for POL converters. The proposed structure creates a piecewise linear synthetic ripple using sensed converter voltages, without the need of direct inductor current sensing. The artificial synthetic ripple is then added to the output voltage and fed as a carrier to the hysteretic comparator, which helps in natural load current feedforward. This proposed digital modulator helps in the reduction of the output capacitors and exhibits superior large-signal dynamics for a POL converter. It is a simple solution and gives immediate fault detection (within one switching cycle) in case of the main switch (top MOSFET) failure of the converter, thus providing adequate protection to the microprocessor load. Analysis, simulation, and experimental results on a 2-V/10-A 20-W single-phase prototype are presented to verify the properties of the proposed modulator.

High breakdown voltage iii-n depletion mode mos capacitors

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.