Showing papers on "Gate oxide published in 1975"

A hydrogen−sensitive MOS field−effect transistor

Abstract: An MOS transistor in silicon with 10−nm silicon dioxide as gate insulator and 10−nm palladium as gate electrode was fabricated. The threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere. At a device temperature of 150 °C it was possible to detect 40 ppm hydrogen gas in air with response times less than 2 min.

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

Abstract: The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the I D -V D characteristics could be simulated by computer model based on the physical effects.

Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states

Abstract: Disclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.

Non-volatile metal nitride oxide semiconductor device

Abstract: A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

Radiation-Induced Defect Centers in Thermally Grown Oxide Films

Abstract: Electron spin resonance and etch-back techniques have been employed to identify radiation-induced defect centers in thermally grown oxide films on SOS wafers and to determine their spatial distribution in the oxide film. The only defect identified was the E' center, which was found to be indistinguishable from E' centers in irradiated bulk fused silica samples. The distribution of E' centers in-oxide films irradiated to a dose of 108 rad (Si) was observed to consist of a uniform bulk distribution plus a concentration build-up near the Si-SiO2 interface. The application of a positive 10 volt bias to a 1.08kA gate oxide during gamma irradiation produced an order of magnitude increase in the E' center concentration.

Self-aligned CMOS process for bulk silicon and insulating substrate device

Abstract: The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

Semiconductor floating gate storage device with lateral electrode system

Abstract: A semiconductor storage device having a field-effect transistor with a floating insulating gate electrode on which information-containing charge can be stored by tunneling charge carriers between the semiconductor body and the gate electrode. According to the invention the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel. Recording and erasing can be carried out at low voltages and with a voltage source of the same polarity relative to a reference potential.

Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+/n) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation

Abstract: A semiconductor memory device comprising a composite structure of semiconductor-insulation layer-floating gate-insulation layer-control gate, in which a periphery of said floating gate is formed to extend up to and immediately above at least one of source and drain regions, such that both overlap each other through the insulation layer therebetween of silicon dioxide and of a thickness of 200 to 400A for more than 0.35 microns in length but not exceeding two times the distance between the source and drain regions. In erasing the contents written in the inventive memory device, a voltage is applied between the substrate and at least one of the source and drain regions in a reverse bias direction with respect to a junction therebetween, while the control gate is supplied with the same potential as that of the substrate or grounded, said erasing voltage being selected to a relatively small value sufficient to cause a Fowler-Nordheim tunnel phenomenon through the first insulation layer between the floating gate and at least one of the source and drain regions at said overlapping area.

Field distribution in junction field-effect transistors at large drain voltages

Abstract: An analytical approximation to the field distribution in the channel portion between gate and drain of the junction field-effect transistor is derived, assuming an infinitely small channel width-to-height ratio, and modified for finite channel widths by introducing an effective impurity concentration which depends on drain current. The approximation is applicable also in the limiting case of zero gate edge curvature, i.e., for Schottky-barrier gate. The theoretical field distribution is used to extract impact-ionization coefficients from published experimental data on gate current enhancement at large drain voltages. These impact-ionization coefficients agree with published data derived from bulk impact ionization.

Effect of silicon-gate resistance on the frequency response of MOS transistors

Abstract: A polycrystalline silicon gate has finite sheet resistivity, typically in the range of tens of ohms per square. The resulting gate resistance and the gate capacitance form a distributed RC network. The gate voltages appearing along this distributed network, hence, the summation drain current, is delayed from the input voltage applied to the contact pad(s). The delay of the distributed RC network is analyzed for both small and large signals. The analysis shows that when the RC time constant of the gate is comparable to the period of the signal, the frequency response is degraded. This time constant varies as the square of the gate width. For a gate width in the fractional millimeter range (typical of output MOS transistors in an integrated circuit), the time constant may be in the 100-ns range; for gate width in the 10-µ range, in the subnanosecond range.

Three mask self aligned IGFET fabrication process

Abstract: A process is disclosed for making a self-aligned IGFET having a polycrystalline silicon gate, using three masking steps. Layers of silicon dioxide, polycrystalline silicon, and silicon nitride are respectively deposited on the surface of a silicon substrate of a first conductivity type. With the first mask, openings are made in regions of these layers above the proposed location for the source and drain. The source and drain are then deposited in the substrate through these openings. The disclosed process continues, growing a silicon dioxide layer on the lateral surfaces of the polysilicon gate, exposed by these openings. Then a silicon nitride layer is deposited on all exposed surfaces and a second mask is employed to permit the removal by etching of this nitride layer from all portions except the proposed location of devices metallization at a first region over the gate, a second region over the source and a third region over the drain of the device. The polycrystalline silicon layer is then etched and removed from the field region of the device. Polysilicon material in the gate region is protected during this etching stop by the first nitride layer and the silicon dioxide layer grown over the lateral exposed surfaces of the gate. The nitride layer regions are then etched away and metallized contacts are formed to the source, drain and polycrystalline silicon gate regions by means of a third and last mask. Alternative steps are disclosed for making the gate and field oxide regions coplanar.

Carrier Injection into SiO2 from Si Surface Driven to Avalanche Breakdown by a Linear Ramp Pulse, and Trapping, Distribution and Thermal Annealing of Injected Holes in SiO2

Abstract: A simple method to produce an avalanche breakdown with a constant avalanche current in the silicon substrate of a MOS diode and to inject hot carriers into the gate oxide is presented. The shift of flatband voltage and that of the breakdown voltage of an n-type MOS diode are observed by hole injection into the gate oxide grown in dry oxygen using the above method. It is observed that about 1/10 of the injected holes could be captured by traps in the gate oxide. It is indicated by both the bias-temperature treatment and the avalanche injection process that hole traps would be generated by avalanche injected holes in the gate oxide. The trapped holes are located near the Si–SiO2 interface decaying from that interface.

Charge cancelling structure and method for integrated circuits

Abstract: According to the invention, the electrical charge which is transferred to a circuit node by the switching ON or OFF of a field effect transistor whose source or drain is connected to that node is cancelled by connecting the source and drain of another field effect transistor to that circuit node and applying to its gate terminal a complement of the switching signal applied to the gate electrode of the first field effect transistor.

Investigation of Radiation Effects and Hardening Procedures for CMOS/SOS

Abstract: Ionizing radiation effects and hardening procedures have been investigated using simple CMOS/SOS circuits fabricated with SiO2 gate insulators. A modified gate oxidation process using steam and HCl has resulted in improved gate oxide hardness -- with threshold voltage shifts of less than two volts up to a total dose of 106 rads(Si). Radiation-induced n-channel leakage currents were reduced by more than two orders of magnitude by using a deep boron ion implant and appropriate process ing techniques. Post-irradiation values of less than 0.5?A/mil have been obtained using this procedure. Studies of charge buildup at the silicon-sapphire interface indicate an effective positive charge in the range of 1011 cm-2 to 1012 cm-2 - peaking at a total dose of about 105 rads (Si). This effective charge decreases for increasing doses above 5×105 rads(Si). The decrease is attributed to radiation-induced interface states.

N-channel MOS transistor

Abstract: An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.

Junction gated field effect transistor

Abstract: A junction gated field effect transistor having a substrate providing a drain region of low impurity concentration, a mosaic shaped gate region of high impurity concentration formed on the drain region, a corresponding mosaic shaped insulating layer overlying said mosaic shaped gate region but having windows therein smaller than the windows of the gate region, the windows of the insulating layer being aligned with the windows of the gate region, a gate electrode connected to said mosaic shaped gate region, a plurality of source regions of high impurity concentration formed on the substrate in the openings of the mesh forming the insulating layer, and a conductive plate source electrode overlying said insulating layer and in contact with said source regions.

Subthreshold slope for insulated gate field-effect transistors

Abstract: An explicit expression has been derived for the subthreshold slope of an insulated gate field-effect transistor. This expression is used to explore the influence of surface band-bending, gate insulator thickness, substrate doping, substrate bias, and temperature.

Junction field effect transistor of vertical type

Abstract: A junction field effect transistor of a vertical type having: a drain region having a first conductivity type; a gate region composed of branches formed on said drain region by a selective vapor deposition or liquidous phase deposition method and having a second conductivity type opposite to the first conductivity type of the drain region, at least that surface of each of the branches of the gate region which locates on the side opposite to the drain region side being covered with an insulating layer; and source regions formed between the respective branches of the gate region by conducting a further growth of said drain region. This field effect transistor has a sufficiently reduced area of P - N junction between the gate region and the respective source regions, resulting in a marked reduction in the junction capacitance. Besides, the insulated gate region with respect to the source regions give rise to a high gate-to-source breakdown voltage property.

Field effect transistor structure and method of making same

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Nonvolatile semiconductor memory devices

Abstract: A nonvolatile semiconductor memory device of the type known as an insulated gate field effect transistor, in which a thick gate insulating layer overlaps the source and drain regions formed in a substrate. The surface of the substrate underlying the thick gate insulating layer is doped lightly with impurities having opposite conductivity relative to the substrate.

Non-volatile memory cell and array using substrate current

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate contact electrode; a means to induce a trapped charge into the gate dielectric layer, including a means to apply a voltage larger than the threshold voltage to the gate electrode to form an inversion layer, and a means to apply a voltage to the drain electrode causing channel current to flow; a means to remove the trapped charge, including a means to apply a voltage equal to or exceeding the avalanche voltage to the drain to cause avalanching; a means to determine the presence or absence of a charge in the gate dielectric including a means to apply a voltage to the gate which is larger than the threshold voltage and a voltage to the drain that is significantly less than the avalanche voltage, and a means to determine the substrate current.

Time dependent breakdown in silicon dioxide films

Abstract: An investigation was conducted regarding the possible existence of a time-dependent breakdown mechanism in thermal oxides of the type used as gate oxide in MOS circuits. Questions of device fabrication are discussed along with details concerning breakdown measurements and the determination of C-V characteristics. A relatively large prebreakdown current observed in one of the cases is related to the time-dependent breakdown.

Schottky gate field effect transistor

Abstract: A Schottky gate field effect transistor of the type comprising a silicon body of one conductivity type on an insulator substrate, and source, drain and gate electrodes is provided with a pn-junction located parallel to the surface of the substrate which produces a space charge zone occupying the zones of the silicon body close to the substrate surface, and a relatively thin active layer is located between the space charge zone and the gate electrode, the active layer having the same type conductivity as the silicon body.

Low transient effect switching device and method

Abstract: A P-channel MOS double gated transistor is provided with an electrical shield element located between the drain and the second gate. The shield is electrically connected to the first gate and is dc biased by the first gate control voltage at FIRST GATE SELECT. The presence of the first gate control voltage causes all the shield capacitances to charge and causes a depletion region between the shield and the drain. Prior to SECOND GATE SELECT, the electrical transient effects of activating the shield with a dc bias have expired. SECOND GATE SELECT introduces new transients (noise current), noteable charging of the capacitance between the drain and the second gate and formation of the final section of depletion region proximate the second gate completing the P channel. This capacitance is drastically reduced by the intervening shield, and the depletion transient is minimized by the priming depletion region established by the shield voltage.

Production of semiconductor device

Abstract: PURPOSE: To obtain an accurate pattern by removing unnecessary Si layer through joint use of vertically reactive spatter etching and unidirectional plasma etching when a gate electrode of multicrystalline Si is formed on a gate oxide film. CONSTITUTION: A thick field oxide film 11' is formed on both ends of an Si substrate 11 and a thin gate oxide film 13 is applied on the surface of the substrate 11 surrounded by said films, and a step 12 comprising portions a, b and c is formed on the border of the films. Then, a polycrystalline Si layer 14 is vapor-grown over the entire surface, where borders a', b' and c' are formed also. Subsequently, with the resist pattern as mask, a vertically reactive spatter etching is applied to the layer 14 employing a CCl 2 F 4 gas leaving a layer 14' true to the dimensions of the pattern 15 without undercut. The layer 14" is removed from the border b' section by unidirectional plasma etching employing CF 4 . With such an arrangement, the desired pattern can be obtained accurately with a high density. COPYRIGHT: (C)1980,JPO&Japio

Multi-channel junction gated field effect transistor and method of making same

Abstract: A multi-channel junction gated field effect transistor which gives good triode characteristics is formed on a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type. A mosaic shape semiconductor gate region of the opposite conductivity type is formed in the substrate below one major surface thereof, the mosaic shape of the gate region forming a plurality of windows filled with portions of the substrate which thus provide channels leading to the main body of the substrate, the main body of the substrate providing the drain region for the transistor. A corresponding relatively thick mosaic shape insulating layer overlies the mosaic shape gate region has a plurality of windows, which windows are smaller than the windows of the gate region and of the same configuration, the windows of the insulating layer being aligned with the windows of the gate region. The source consists of two regions, one which is heavily doped with impurity of the first conductivity type and the second which has less doping than that of the first source region but of greater doping than the drain region and the channel regions. The first source region is completely within the windows of the insulating layer, while the second source region is partially within such windows and extends down as a tongue partially into the channel. Electrodes are provided for the source, gate and drain regions. The substrate is preferably N-type silicon having a doping level of 1014 to 1015 atoms/cm3. The first source region preferably has a doping higher than 5 × 1019, while the second source region with its tongues has a doping level between 1016 and 1018 atoms/cm3. If the doping level of the second source region is 1018 atoms/cm3, it is possible to have the substrate doped to 1016 atoms/cm3.

Semiconductor device including a conductor surrounded by an insulator

Abstract: A silicon-gate insulated gate field effect transistor device has a thick field oxide in contiguous surrounding relation to its gate electrode and with a surface coplanar with or slightly higher than the surface of the gate electrode, thus facilitating crossovers and contacts to the gate electrode. The method of making this device includes forming a self-aligned silicon gate structure on a silicon wafer, masking the gate structure against the diffusion of oxygen, and thereafter oxidizing the silicon wafer to grow a thick silicon dioxide layer in surrounding relation to the silicon gate structure.

Method of simultaneously forming a polycrystalline silicon gate and a single crystal extension of said gate in silicon on sapphire MOS devices

Abstract: An improvement in polycrystalline silicon gate MOS integrated circuits made of silicon mesas on a sapphire substrate is provided. The improvement is an extension of a polycrystalline silicon gate onto the sapphire substrate as a single crystal layer. The single crystal layer is anisotrophically etched to slant its sidewalls. Metal contacts traversing the slanted sidewalls exhibit increased continuity and the single crystal layer exhibits improved conductivity. The polycrystalline silicon and single crystal silicon are formed simultaneously from a single source.

Negative resistance network

Abstract: This negative resistance network includes a first predetermined channel insulated gate enhancement type field effect transistor having a drain-source path connected to positive and negative input terminals on which a predetermined input voltage is impressed. The gate potential of the first field effect transistor is controlled by a second insulated gate enhancement type field effect transistor having an opposite channel type to the first field effect transistor, a gate connected to the drain thereof which is connected to the predetermined one of the positive and negative input terminals and a source connected to one pole of a dc power supply having a predetermined voltage, and by a third insulated gate enhancement type field effect transistor having the same channel type as the first field effect transistor, a drain and a gate connected to the drain of the second field effect transistor as well as to the gate of the first field effect transistor and a source connected to the source thereof which is connected to the other input terminal as well as to the other pole of the dc power supply, whereby the first field effect transistor shows a negative resistance characteristic attaining a relatively low current consumption over a relatively wide level range of the input voltage.