Showing papers on "Latency (engineering) published in 1995"

Dynamic Server Selection In The Internet

Abstract: As distributed information services like the World Wide Web become increasingly popular on the Internet, problems of scale are clearly evident. A promising technique that addresses many of these problems is service (or document) replication. However, when a service is replicated, clients then need the additional ability to find a ``good'''' provider of that service. In this paper we report on techniques for finding good service providers without a priori knowledge of server location or network topology. We consider the use of two principal metrics for measuring distance in the Internet: hops, and round-trip latency. We show that these two metrics yield very different results in practice. Surprisingly, we show data indicating that the number of hops between two hosts in the Internet is {\em not\/} strongly correlated to round-trip latency. Thus, the distance in hops between two hosts is not necessarily a good predictor of the expected latency of a document transfer. Instead of using known or measured distances in hops, we show that the extra cost at runtime incurred by dynamic latency measurement is well justified based on the resulting improved performance. In addition we show that selection based on dynamic latency measurement performs much better in practice that any static selection scheme. Finally, the difference between the distribution of hops and latencies is fundamental enough to suggest differences in algorithms for server replication. We show that conclusions drawn about service replication based on the distribution of hops need to be revised when the distribution of latencies is considered instead.

Retrieval from semantic memory and its implications for Alzheimer's disease.

Abstract: In 3 experiments, participants generated category exemplars (e.g., kinds of fruits) while a voice key and computer recorded each response latency relative to the onset of responding. In Experiment 1, mean response latency was faster when participants generated exemplars from smaller categories, suggesting that smaller mental search sets result in faster mean latencies. In Experiment 2, a concurrent secondary task increased mean response latency, suggesting that slowed mental processing results in slower mean latencies. In Experiment 3, the mean response latency of Alzheimer's participants was faster than that of elderly controls, which is consistent with the idea that the semantic memory impairments of Alzheimer's disease patients stem primarily from a reduction in available items (as in Experiment 1) rather than retrieval slowing (as in Experiment 2).

A Comparison Between House Mouse Lines Selected for Attack Latency or Nest-Building: Evidence for a Genetic Basis of Alternative Behavioral Strategies

Abstract: House mouse lines bidirectionally selected for either nest-building behavior or attack latency were tested for both attack latency and nest-building behavior under identical conditions. Male mice selected for high nest-building behavior had shorter attack latencies, i.e., were more aggressive, than those selected for low nest-building behavior and their randomly bred control lines. Conversely, male wild house mice selected for short attack latency showed more nest-building behavior than those selected for long attack latency when tested at 110 days of age. These findings imply a common genetic basis for control of aggression and nesting and support earlier proposals as to how animals may exhibit fundamentally different responses to environmental challenges, either reacting actively to aversive situations (aggressive and high-nesting animals: active copers) or adopting a passive strategy (nonaggressive and low-nesting animals: passive copers).

The Effects of Latency, Occupancy, and Bandwidth in Distributed Shared Memory Multiprocessors

Abstract: Distributed shared memory (DSM) machines can be characterized by four parameters, based on a slightly modified version of the logP model. The l (latency) and o (occupancy of the communication controller) parameters are the keys to performance in these machines, and are largely determined by major architectural decisions about the aggressiveness and customization of the node and network. For recent and upcoming machines, the g (gap) parameter that measures node-to-network bandwidth does not appear to be a bottleneck. Conventional wisdom is that latency is the dominant factor in determining the performance of a DSM machine. We show, however, that controller occupancy--which causes contention even in highly optimized applications--plays a major role, especially at low latencies. When latency hiding is used, occupancy becomes more critical, even in machines with high latency networks. Scaling the problem size is often used as a technique to overcome limitations in communication latency and bandwidth. We show that in many structured computations occupancy-induced contention is not alleviated by increasing problem size, and that there are important classes of applications for which the performance lost by using higher latency networks or higher occupancy controllers cannot be regained easily, if at all, by scaling the problem size.

Method and apparatus for multiple latency synchronous pipelined dynamic random access memory

Abstract: A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes. Also, in three latency operation, data is clocked along a data input path with a write latency. The multiple latency synchronous dynamic random access memory includes a pair of output data paths having different delays, where the data path is selected according to two or three latency operation.

Combatting rendering latency

Abstract: Latency or lag in an interactive graphics system is the delay between user input and displayed output. We have found latency and the apparent bobbing and swimming of objects that it produces to be a serious problem for head-mounted display (HMD) and augmented reality applications. At UNC, we have been investigating a number of ways to reduce latency; we present two of these. Slats is an experimental rendering system for our Pixel-Planes 5 graphics machine guaranteeing a constant single NTSC field of latency. This guaranteed response is especially important for predictive tracking. Just-in-time pixels is an attempt to compensate for rendering latency by rendering the pixels in a scanned display based on their position in the scan.

Totally Ordered Multicast in Large-Scale Systems

Abstract: Totally ordered multicast protocols have proved to be extremely useful in supporting fault-tolerant distributed applications. This paper compares the performance of the two main classes of protocols providing total order in large-scale systems: token-site and symmetric protocols. The paper shows that both classes of protocols can exhibit a latency close to 2D, where D is the message transit delay between two processes. In the face of these observations, the paper makes the following contributions: it presents a rate-synchronization scheme for symmetric protocols that exhibits a latency close to D+t, where t is the inter-message transmission time; it proposes a new hybrid protocol and shows that the hybrid scheme for heterogeneous topologies performs better than any of the previous classes of protocols in isolation; finally, the paper presents an algorithm that allows a process to dynamically adapt to changes in throughput and in network delays. The combination of these three techniques results in a dynamic hybrid scheme that, when applied to systems where the topology/traffic patterns are not known a priori, offers a much lower latency than non-hybrid approaches.

Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput

Abstract: Although throughput alone can be arbitrarily improved for several classes of systems using previously published techniques, none of those approaches are effective when latency constraints, which are increasingly important in embedded DSP systems, are considered. After formally establishing the relationship between latency and throughput in general computation, we explore the effect of pipelining on latency, and establish necessary and sufficient conditions under which pipelining does not alter latency. Many systems are either linear, or have subsystems that are linear. For such cases we have used a state-space based approach that treats various transformations in an integrated fashion, and answers analytically whether it is possible to simultaneously meet any given combination of constraints on latency and throughput, The analytic approach is constructive in nature, and produces a complete implementation when feasibility conditions are fulfilled. We also present a suboptimal but hardware efficient heuristic approach for the special case of initially-relaxed single-input single-output linear time-invariant computations. A novel software platform consisting of a high-level synthesis system coupled to a symbolic algebra system was used to implement the proposed algorithm transformations. Instead of optimizing to improve throughput and latency, our transformations can also be used to increase the implementation efficiency while achieving the same latency and throughput as the original design. >

On Checkpoint Latency

Abstract: Checkpointing and rollback is a technique to minimize the loss of computation in the presence of failures. Two metrics can be used to characterize a checkpointing scheme: (i) checkpoint overhead (increase in the execution time of the appliction because of a checkpoint), and (ii) checkpoint latency (duration of time required to save the checkpoint). The contributions of this report are as follows: 1. The report evaluates the expression for average overhead of the recovery scheme as a function of checkpoint latency and overhead. 2. A mechanism that attempts to reduce checkpoint overhead usually causes an increase in the checkpoint latency. A decrease in checkpoint overhead can result in an increase or a decrease in the average overhead, depending on whether the latency is increased "too much" or not. This report determines a function g of checkpoint overhead C such that checkpoint latency should be less that g(C) to achieve a decrease in the average overhead. 3. For equi-distant checkpoints, the optimal checkpoint interval is shown to be independent of the checkpoint latency (L).

An Analysis of Division Algorithms and Implementations

Abstract: Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications. However, the increasing emphasis on high performance graphics and the industry-wide usage of performance benchmarks forces processor designers to pay close attention to all aspects of floating-point computation. Many algorithms are suitable for implementing division in hardware. This paper presents four major classes of algorithms in a unified framework, namely digit recurrence, functional iteration, very high radix, and variable latency. Digit recurrence algorithms, the most common of which is SRT, use subtraction as the fundamental operator, and they converge to a quotient linearly. Division by functional iteration converges to a quotient quadratically using multiplication. Very high radix division algorithms are similar to digit recurrence algorithms, but they incorporate multiplication to reduce the latency. Variable latency division algorithms reduce the average latency to form the quotient. These algorithms are explained and compared in this work. It is found that for low-cost implementations where chip area must be minimized, digit recurrence algorithms are suitable. An implementation of division by functional iteration can provide the lowest latency for typical multiplier latencies. Variable latency algorithms show promise for simultaneously minimizing average latency while also minimizing area.

Issues and Implications

Abstract: This chapter contains sections titled: Why Consider Petaflops Now?, Role of a Petaflops Computer, Side-effect Products, Impact of Exotic Technologies, Performance Versus Efficiency, Programming Paradigms, U.S. Capabilities in Memory Fabrication, Special Widgets, Where to Invest, A Range of Architectures, Far-side Architectures, Latency Hiding Techniques, Long versus Short Latency Machines, SIA Predictions, I/O Scaling

Method and apparatus for automatic selection of the load latency to be used in modulo scheduling in an optimizing compiler

Abstract: Apparatus and methods are disclosed for determining a load latency value to use in scheduling instructions for a target program, (the load latency value is the separation between a load command and the using instruction, wherein the expected return of the data is a function of where in the system the requested data resides). The instruction scheduling function is the modulo scheduling function of an optimizing compiler. Most modem microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units and typically multi-level memory devices such as on-chip cache, off-chip cache as well as main memory. For such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduling loops in the target program code. The invention consists of a technique to determine an optimal load latency value given an rmii vector, which is a set of rmii values which correspond to different values of instruction load latency. The disclosed invention makes the determination of the optimal load latency an automatic feature of the optimizing compiler thereby not requiring the user to specify the load latency and or change the specified load latency values if the target program is to be recompiled to run on a different target computer platform.

HSV as a gene transfer vector for the nervous system.

Abstract: Gene therapy for diseases of the nervous system requires vectors capable of delivering the therapeutic gene into postmitotic cells in vivo. Herpes simplex virus type 1 is a neurotropic virus that naturally establishes latency in neurons of the peripheral nervous system. Replication defective HSV vectors have been developed; these are deleted for at least one essential immediate early regulatory gene, rendering the virus less cytotoxic, incapable of reactivation, but still capable of establishing latency. Foreign genes can be vigorously expressed from an HSV-based vector in a transient manner in brain and other tissues. Long-term but weak foreign gene expression may be achieved in the nervous system by exploiting the transcriptional control mechanisms of the natural viral latency active promoter. To meet the needs of specific applications, either highly active long-term or regulatable transgene expression will be needed, requiring further studies in order to design the appropriate latency-based promoter systems.

Data output buffer of semiconductor memory device

Abstract: The data output buffer of a semiconductor memory device which uses a clock externally applied at a constant cycle, comprises a delay circuit which has first and second delay time cycles and outputs first and second delay signals; a selection circuit for inputting the first and second delay signals and selecting one of the first and second delay signals according to a predetermined signal; and a data output buffer for outputting data according to the selected delay signal and a latency information signal.

System effects of interprocessor communication latency in multicomputers

Abstract: A series of experiments and analyses on five types of hypercube and grid-topology multicomputers, carried out to evaluate interprocessor communication performance, is described. The effects on the system of communication speed, message routing, interprocessor connectivity, and message-passing software/hardware protocols were studied. The experimental results clearly show the difference in interprocessor communication performance between the first-generation multicomputer systems and the second-generation distributed multiprocessor systems. The traditional store-and-forward technique for interprocessor communication greatly limits the communication speed among the processors. In addition, the processors of the first-generation systems are not very powerful, which is another major reason communication proceeds slowly in these systems. It is seen that the wormhole routing model greatly reduces communication latency and is not sensitive to the distance involved in passing messages. >

A 3D tracking experiment on latency and its compensation methods in virtual environments

Abstract: In this paper, we conducted an experiment on the latency and its compensation methods in a virtual reality application using an HMD and a 3D head tracker. Our purpose is to make a comparison both in the simulation and in the real task among four tracker prediction methods: the Grey system theory based prediction proposed in 1994. the Kalman filtering which is well-known and widespreading since 1991, a simple linear extrapolation. and the basic method without prediction. In our 3D target tracing task that involved eight subjects, who used their head motion to trace a flying target in random motion, we have found that when the system latency is 120ms. two prediction methods, Kalman filtering (not inertial-based) and Grey system prediction, are significantly better than the one without prediction, and the former two methods are equally well in performance. Typical motion trajectories of four methods in simulation are plotted, and jittering effects are examined. In terms of jittering at 120ms prediction length, Kalman filtering was evaluated to have the largest.

Dual mode arbitration apparatus and method for reducing latency by allowing the possibility of simultaneous request and access for a shared bus

Abstract: A method and apparatus for reducing arbitration latency. A fast mode is defined to allow simultaneous request and access to a shared resource. A slow mode is defined to require a request, followed by arbitration, followed by access to the resource. By dynamically switching between fast and slow modes responsive to the volume of requests received, arbitration latency is reduced.

Method and apparatus for masking latency in an interactive television network

Abstract: A method and apparatus for masking latency in an interactive television network. One embodiment of the invention initially receives a command pertaining to an interactive selection from a viewer. The invention then determines if latency is associated with the execution of the received command. If so, the invention (1) begins processing the command, and (2) presents a latency-masking presentation.

Algebraic survivor memory management design for Viterbi detectors

Abstract: The problem of survivor memory management of a Viterbi detector is classically solved either by a register-exchange implementation which has minimal latency, but large hardware complexity and power consumption, or by a trace-back scheme with small power consumption, but larger latency. Here an algebraic formulation of the survivor memory management is introduced which provides a framework for the derivation of new algorithmic and architectural solutions. This allows for solutions to be designed with greatly reduced latency and/or complexity, as well as for achieving tradeoff between latency and complexity. VLSI case studies of specific new solutions have shown that at minimal latency more than 50% savings are possible in hardware complexity as well as power consumption. >

A method and system for reducing dispatch latency in a processor

Abstract: A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.

Studies on wild house mice (VIII): Postnatal maternal influences on intermale aggression in reciprocal F1's.

Abstract: Previous findings have shown a difference in attack latencies, i.e., aggression, between reciprocal F1's of a line selected for short attack latency (SAL) and a line selected for long attack latency (LAL). In the present study, we investigated the influence of postnatal maternal environment on attack latency scores (ALSs). The results show that only the evolution of the ALSs over 3 consecutive days is influenced by crossfostering. Accordingly, we conclude that the postnatal maternal environment affects ALSs only to a small extent.

Modeling virtual channel flow control in hypercubes

Abstract: An analytical model for virtual channel flow control in n-dimensional hypercubes using the e-cube routing algorithm is developed. The model is based on determining the values of the different components that make up the average message latency. These components include the message transfer time, the blocking delay at each dimension, the multiplexing delay at each dimension, and the waiting delay at the source node. The first two components are determined using a probabilistic analysis. The average degree of multiplexing is determined using a Markov model, and the waiting delay at the source node is determined using an M/M/m queueing system. The model is fairly accurate in predicting the average message latency for different message sizes and a varying number of virtual channels per physical channel. It is demonstrated that wormhole switching along with virtual channel flow control make the average message latency insensitive to the network size when the network is relatively lightly loaded (message arrival rate is equal to 40% of channel capacity), and that the average message latency increases linearly with the average message size. The simplicity and accuracy of the analytical model make it an attractive and effective tool for predicting the behavior of n-dimensional hypercubes. >

Discriminative power of visual evoked potential characteristics in multiple sclerosis

Abstract: To investigate the discriminative power of pattern-reversal visual evoked potential characteristics (peak latencies and amplitude) and to test whether the addition of visual evoked potential amplitude can increase the power of the visual evoked potential in the diagnosis of multiple sclerosis, we retrospectively studied visual evoked potentials in 59 patients with definite multiple sclerosis and 126 control subjects. Two check sizes (17' and 10') were used. Females had significantly higher amplitudes and shorter latencies than males. N80 latency showed a gradual increase and P100 amplitude a decrease with age. P100 latency was stable between the ages of 20 and 55 years but was increased in childhood and the elderly. The significance of visual evoked potential peak latencies and amplitude in separating the two groups was investigated by means of a (multivariate) discriminant analysis. The visual evoked potential with a pattern of 10' could be measured in 58% of patients with multiple sclerosis. The exclusive use of the P100 amplitude in the discriminant analysis resulted in a percentage of correctly classified cases of 84%, whereas for P100 and N80 latency it was 85% and 90%, respectively. With the 17' pattern, the N80 latency yielded also a higher correct percentage than did the P100 latency. Although N80 latency is, to a greater extent than P100 latency, influenced by age, sex and size of stimulus pattern, when these influences are accounted for, the N80 latency is a more sensitive measure than P100 latency in the classification of multiple sclerosis. Combined use of latency and amplitude for discriminant analysis yielded no significant improvement of the percentage of correctly classified cases.

Implementing communication latency hiding in high-latency computer networks

Abstract: We present a latency hiding protocol for asynchronous message passing in UNIX environments With this protocol distributed parallel computing can be utilized to solve applications, which can be structured such that useful computation overlaps communication, in a more efficient way than possible with current standard technologies To maintain portability our protocol is layered on top of the Berkeley socket interface and the TCP/IP protocol We present experimental data that validate our model on latency hiding and demonstrate the capability of our implementation