Showing papers on "Latency (engineering) published in 2014"

Real-time and low latency embedded computer vision hardware based on a combination of FPGA and mobile CPU

Abstract: Recent developments in smartphones create an ideal platform for robotics and computer vision applications: they are small, powerful, embedded devices with low-power mobile CPUs. However, though the computational power of smartphones has increased substantially in recent years, they are still not capable of performing intense computer vision tasks in real time, at high frame rates and low latency. We present a combination of FPGA and mobile CPU to overcome the computational and latency limitations of mobile CPUs alone. With the FPGA as an additional layer between the image sensor and CPU, the system is capable of accelerating computer vision algorithms to real-time performance. Low latency calculation allows for direct usage within control loops of mobile robots. A stereo camera setup with disparity estimation based on the semi global matching algorithm is implemented as an accelerated example application. The system calculates dense disparity images with 752×480 pixels resolution at 60 frames per second. The overall latency of the disparity estimation is less than 2 milliseconds. The system is suitable for any mobile robot application due to its light weight and low power consumption.

System and method for investigating large amounts of data

Abstract: A data analysis system is proposed for providing fine-grained low latency access to high volume input data from possibly multiple heterogeneous input data sources. The input data is parsed, optionally transformed, indexed, and stored in a horizontally-scalable key-value data repository where it may be accessed using low latency searches. The input data may be compressed into blocks before being stored to minimize storage requirements. The results of searches present input data in its original form. The input data may include access logs, call data records (CDRs), e-mail messages, etc. The system allows a data analyst to efficiently identify information of interest in a very large dynamic data set up to multiple petabytes in size. Once information of interest has been identified, that subset of the large data set can be imported into a dedicated or specialized data analysis system for an additional in-depth investigation and contextual analysis.

Achieving low latency and energy consumption by 5G TDD mode optimization

Abstract: The target for a new 5G radio access technology is to support multi-Gbps and ms latency connectivity simultaneously at noticeably lower energy consumption and cost compared to the existing 4G technologies, such as LTE-Advanced. Extremely short air interface latency is required to achieve these requirements in a TDD-based local area network. In this paper, we discuss how the required short TDD latency can be achieved and further utilized in 5G physical air interface. First, we investigate the enablers and limits of TDD latency by analyzing the performance of OFDM in different channel environments and discussing on the consequent frame length limits. We then provide a description on how the achieved short TDD latency can further be utilized to enable remarkably low energy consumption. A numerical analysis comparing the battery life time of the suggested 5G TDD air interface and LTE is provided, showing remarkable gains for the 5G air interface concept.

Low latency stabilization for head-worn displays

Abstract: Methods, systems, and computer readable media for low latency stabilization for head-worn displays are disclosed. According to one aspect, the subject matter described herein includes a system for low latency stabilization of a head-worn display. The system includes a low latency pose tracker having one or more rolling-shutter cameras that capture a 2D image by exposing each row of a frame at a later point in time than the previous row and that output image data row by row, and a tracking module for receiving image data row by row and using that data to generate a local appearance manifold. The generated manifold is used to track camera movements, which are used to produce a pose estimate.

LASER: a scalable response prediction platform for online advertising

Abstract: We describe LASER, a scalable response prediction platform currently used as part of a social network advertising system. LASER enables the familiar logistic regression model to be applied to very large scale response prediction problems, including ones beyond advertising. Though the underlying model is well understood, we apply a whole-system approach to address model accuracy, scalability, explore-exploit, and real-time inference. To facilitate training with both large numbers of training examples and high dimensional features on commodity clustered hardware, we employ the Alternating Direction Method of Multipliers (ADMM). Because online advertising applications are much less static than classical presentations of response prediction, LASER employs a number of techniques that allows it to adapt in real time. LASER models can be divided into components with different re-training frequencies, allowing us to learn from changes in ad campaign performance frequently without incurring the cost of retraining larger, more stable sections of the model. Thompson sampling during online inference further helps by efficiently balancing exploration of new ads with exploitation of long running ones. To enable predictions made with the most recent feature data, we employ a range of techniques, including extensive caching and lazy evaluation, to permit real time, low latency scoring. LASER models are defined using a configuration language that ties together the training, validation, and inference pieces and permits even non-programming analysts to experiment with different model structures without modifications to code or interruptions to running servers. Finally, we show via extensive offline experiments and online A/B tests that this system provides significant benefits to prediction accuracy, gains in revenue and CTR, and reductions in system latency.

Methods and Systems for High Bandwidth Chip-to-Chip Communications Interface

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values

SDN-controlled topology-reconfigurable optical mobile fronthaul architecture for bidirectional CoMP and low latency inter-cell D2D in the 5G mobile era.

Abstract: We demonstrate the first SDN-controlled optical topology-reconfigurable mobile fronthaul (MFH) architecture for bidirectional coordinated multipoint (CoMP) and low latency inter-cell device-to-device (D2D) connectivity in the 5G mobile networking era. SDN-based OpenFlow control is used to dynamically instantiate the CoMP and inter-cell D2D features as match/action combinations in control plane flow tables of software-defined optical and electrical switching elements. Dynamic re-configurability is thereby introduced into the optical MFH topology, while maintaining back-compatibility with legacy fiber deployments. 10Gb/s peak rates with <7μs back-to-back transmission latency and 29.6dB total power budget are experimentally demonstrated, confirming the attractiveness of the new approach for optical MFH of future 5G mobile systems.

Low latency query engine for apache hadoop

Abstract: A low latency query engine for Apache Hadoop that provides real-time or near real-time, ad hoc query capability, while completing batch-processing of MapReduce. In one embodiment, the low latency query engine comprises a daemon that is installed on data nodes in a Hadoop cluster for handling query requests and all internal requests related to query execution. In a further embodiment, the low latency query engine comprises a daemon for providing name service and metadata distribution. The low latency query engine receives a query request via client, turns the request into collections of plan fragments and coordinates parallel and optimized execution of the plan fragments on remote daemons to generate results at a much faster speed than existing batch-oriented processing frameworks.

Pipelineable On-line Encryption

Abstract: Correct authenticated decryption requires the receiver to buffer the decrypted message until the authenticity check has been performed. In high-speed networks, which must handle large message frames at low latency, this behavior becomes practically infeasible. This paper proposes CCA-secure on-line ciphers as a practical alternative to AE schemes since the former provide some defense against malicious message modifications. Unfortunately, all published on-line ciphers so far are either inherently sequential, or lack a CCA-security proof.

Self-clocked rate adaptation for conversational video in LTE

Abstract: This paper describes a rate adaptation framework for conversational video services. The solution conforms to the packet conservation principle and uses a hybrid loss and delay based congestion control algorithm. The framework is evaluated over both simulated bottleneck scenarios as well as in a LTE system simulator and is shown to achieve both low latency and high video throughput in these scenarios, something that improves the end user experience.

Low-Latency ECDSA Signature Verification - A Road Towards Safer Traffic -.

Abstract: Car-to-car and Car-to-Infrastructure messages exchanged in Intelligent Transportation Systems can reach reception rates up to and over 1000 messages per second. As these messages contain ECDSA signatures this puts a very heavy load onto the verification hardware. In fact the load is so high that currently it can only be achieved by implementations running on high end CPUs and FPGAs. These implementations are far from cost-effective nor energy efficient. In this paper we present an ASIC implementation of a dedicated ECDSA verification engine that can reach verification rates of up to 27.000 verifications per second using only 1.034 kGE.

Low latency radio interface for 5G flexible TDD local area communications

Abstract: This paper presents a low latency radio interface design for future 5G local area communications that provides transmission latencies less than 1 ms while providing sufficient spectral efficiency. We concentrate on the excellent latency aspects of the proposed 5GETLA radio interface and discuss the factors leading to very low latency and high energy efficiency. In addition, we study two different radio interface parameterizations and compare their total overheads and achievable transmission times.

High rate, low-latency multi-touch sensing with simultaneous orthogonal multiplexing

Abstract: We present "Fast Multi-Touch" (FMT), an extremely high frame rate and low-latency multi-touch sensor based on a novel projected capacitive architecture that employs simultaneous orthogonal signals. The sensor has a frame rate of 4000 Hz and a touch-to-data output latency of only 40 microseconds, providing unprecedented responsiveness. FMT is demonstrated with a high-speed DLP projector yielding a touch-to-light latency of 110 microseconds.

Background format optimization for enhanced SQL-like queries in Hadoop

Abstract: A format conversion engine for Apache Hadoop that converts data from its original format to a database-like format at certain time points for use by a low latency (LL) query engine. The format conversion engine comprises a daemon that is installed on each data node in a Hadoop cluster. The daemon comprises a scheduler and a converter. The scheduler determines when to perform the format conversion and notifies the converter when the time comes. The converter converts data on the data node from its original format to a database-like format for use by the low latency (LL) query engine.

Surveillance video analysis using compressive sensing with low latency

Abstract: We propose a method for analysis of surveillance video by using low rank and sparse decomposition (LRSD) with low latency combined with compressive sensing to segment the background and extract moving objects in a surveillance video. Video is acquired by compressive measurements, and the measurements are used to analyze the video by a low rank and sparse decomposition of a matrix. The low rank component represents the background, and the sparse component, which is obtained in a tight wavelet frame domain, is used to identify moving objects in the surveillance video. An important feature of the proposed low latency method is that the decomposition can be performed with a small number of video frames, which reduces latency in the reconstruction and makes it possible for real time processing of surveillance video. The low latency method is both justified theoretically and validated experimentally.

Overview on initial METIS D2D concept

Abstract: METIS is the EU flagship project with the purpose of developing a 5G system concept that meets the requirements of the beyond-2020 connected information society and emerging applications Within METIS project, horizontal topics (HTs) are used to build the overall system concept Direct Device-to-Device (D2D) communication is one of the HTs and regarded as a promising technology to provide low power, high data rate and low latency services between end-users in the future 5G networks This paper presents an initial view on the HT D2D concept In addition, the performance of selected technology components is included in this paper as well

A hybrid MAC protocol for emergency response wireless sensor networks

Abstract: We introduce ER-MAC, a novel hybrid MAC protocol for emergency response wireless sensor networks. It tackles the most important emergency response requirements, such as autonomous switching from energy-efficient normal monitoring to emergency monitoring to cope with heavy traffic, robust adaptation to changes in the topology, packet prioritisation and fairness support. ER-MAC is designed as a hybrid of the TDMA and CSMA approaches, giving it the flexibility to adapt to traffic and topology changes. It adopts a TDMA approach to schedule collision-free slots. Nodes wake up for their scheduled slots, but otherwise switch into power-saving sleep mode. When an emergency occurs, nodes that participate in the emergency monitoring change their MAC behaviour by allowing contention in TDMA slots to achieve high delivery ratio and low latency. In its operation, ER-MAC prioritises high priority packets and sacrifices the delivery ratio and latency of the low priority ones. ER-MAC also guarantees fairness over the packets’ sources and offers a synchronised and loose slot structure to allow nodes to join or leave the network. Simulations in ns-2 show the superiority of ER-MAC over Z-MAC, a state-of-the art hybrid MAC protocol, with higher delivery ratio, lower latency, and lower energy consumption. When a cluster of nodes in the network detects fire, nodes with ER-MAC deliver twice as many high priority emergency packets and four times faster than Z-MAC. This is achieved by ER-MAC with only one fifth as much energy as Z-MAC.

Low latency communication infrastructure for synchrophasor applications in distribution networks

Abstract: With the introduction of new power sources, such as distributed renewable energy resources, and loads, such as electric vehicles, electrical distribution networks must accommodate new energy flow patterns in a considerably dynamic environment. This leads to the need for increasing the observability of the grid to enable a series of mission-critical applications such as voltage/congestion control and fault detection/location. The deployment of Phasor Measurement Units appears to be a promising approach, offering high precision grid monitoring. However, while the low delay requirements of such applications raise a significant challenge to the communication infrastructure, there is currently no clear vision on the exact communication technologies and network topologies that could support these requirements. In this paper, we address this challenge by taking a systematic approach on the design of low latency communication infrastructures. Based on a large set of real medium voltage grid topologies from a European distribution network, we first perform a detailed analysis of the communication requirements. Guided by this analysis, we then propose two algorithms, PLeC and BW-PLeC algorithms, for the design of low latency communication infrastructures that enhance the currently available power-line communication technology with newer high-speed communication links at strategic points in the grid to satisfy the delay requirements while reducing deployment costs.

On the flexible 5G dense deployment air interface for mobile broadband

Abstract: In this paper we contemplate 5G frame structure for dense deployment. We discuss harmonized OFDM concept, in which the cyclic prefix length and subcarrier spacing are functions of carrier frequency while FFT size and base clock remain constant. The subframe structure consists of time separated control and data, enabling low latency, flexible UL/DL ratio switching and high spectral efficiency with low cost transceiver. Analysis shows that the overheads are relatively small. The subframe structure also allows extended sleep periods, enabling considerably reduced power consumption.

Low latency live video streaming

Abstract: Techniques are disclosed for low latency live video streaming. A client can be configured to send a single HTTP request for live video streaming to a server. The server can be configured to push one or more video segments to the client in response to the request, following a pre-defined push strategy. For example, using a so-called all-push strategy, the client sends only one request to the server, and in response, the server sends all of the video segments to the client as soon as each segment is complete. The HTTP 2.0 protocol may be used for pushing the video from the server to the client. This technique eliminates the request explosion problem when small segments are used. Further, the number of segments pushed with each request can be varied, which is to facilitate adaptive bitrate switching.

Porting locally processed media data with low latency to a remote client device via various wireless links

Abstract: Systems, methods, and computer-readable media for porting locally processed media data with low latency to a remote client device via various wireless links are provided. In one example embodiment, a transceiver module may include a local network interface and a controller that may receive a client control signal from a client device over a wireless local area network via the local network interface, transmit a media control signal based on the client control signal to a media device, receive media data based on the media control signal from the media device, and transmit to the client device over the wireless local area network via the local network interface client data based on the media data and a low-latency compression technique. The receipt of the media data and transmission of the client data may be accomplished with substantially no detectable latency. Additional embodiments are also provided.

Initial MAC Exploration for Graphene-enabled Wireless Networks-on-Chip

Abstract: In the upcoming many-core era, chip multiprocessor architectures will be composed of hundreds or even thousands of processor cores, which interact among them through an on-chip communication platform for synchronization and data coherency/consistency purposes. As the traffic generated within the chip becomes more multicast-intensive, it is necessary to conceive novel communication platforms that go beyond conventional schemes and guarantee multicast support with high throughput, low latency, and low power. Nanotechnology provides an opportunity within this context by virtue of terahertz graphene antennas, which could allow the integration of one antenna per core in a Graphene-enabled Wireless Network-on-Chip (GWNoC). However, it is essential to design an appropriate MAC protocol in order to fully benefit from this novel approach. To provide a first contribution in this direction, in this paper we design two baseline MAC protocols based on the well-known ALOHA and carrier sensing techniques. Their functionalities have been properly conceived by taking into account characteristics and requirements of future chip multiprocessors systems. Moreover, their performances have been evaluated by means of computer simulations under different chip configurations. Obtained results demonstrate the pros and cons of these simple contention-based MAC protocols and pave the way for the future exploration of the MAC design space.

3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time

Abstract: This paper introduces 3D-Wiz, which is a high bandwidth, low latency, optically interfaced 3D DRAM architecture with fine grained data organization and activation. 3D-Wiz integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus using TSVs and fan-out buffers enables 3D-Wiz to use smaller dimension subarrays without significant area overhead. This in turn reduces the random access latency and activation-precharge energy. 3D-Wiz demonstrates access latency of 19.5ns and row cycle time of 25ns. It yields per access activation energy and precharge energy of 0.78nJ and 0.62nJ respectively with 42.5% area efficiency. 3D-Wiz yields the best latency and energy consumption values per access among other well-known 3D DRAM architectures. Experimental results with PARSEC benchmarks indicate that 3D-Wiz achieves 38.8% improvement in performance, 81.1% reduction in power consumption, and 77.1% reduction in energy-delay product (EDP) on average over 3D DRAM architectures from prior work.

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture

Abstract: Memory speed has become a major performance bottleneck as more and more cores are integrated on a multi-core chip. The widening latency gap between high speed cores and memory has led to the evolution of multi-level SRAM/DRAM cache hierarchies that exploit the latency benefits of smaller caches (e.g. private L1 and L2 SRAM caches) and the capacity benefits of larger caches (e.g. shared L3 SRAM and shared L4 DRAM cache). The main problem of employing large L3/L4 caches is their high tag lookup latency. To solve this problem, we introduce the novel concept of small and low latency SRAM/DRAM Tag-Cache structures that can quickly determine whether an access to the large L3/L4 caches will be a hit or a miss. The performance of the proposed Tag-Cache architecture depends upon the Tag-Cache hit rate and to improve it we propose a novel Tag-Cache insertion policy and a DRAM row buffer mapping policy that reduce the latency of memory requests. For a 16-core system, this improves the average harmonic mean instruction per cycle throughput of latency sensitive applications by 13.3% compared to state-of-the-art.

IEEE 802.15.4e LLDN: Superframe configuration for networked control systems

Abstract: Wireless networked control systems have gained significant popularity due to commissioning and maintenance ease. Currently there are various wireless communication protocols available to accomplish the control networks. Recently, IEEE 802.15.4e protocol for low latency deterministic network has been introduced that shows prominent theoretical characteristics under effective frequency planning to minimize mutual interference. Factory automation, highly exacting from low latency point of view, requires sensors refresh rate not more than of order 10 milliseconds. This new protocol meets such stringent requirement of industrial automation systems. In this paper, we compare the new protocol with its previous version and observe its suitability for industrial networked control systems as a communication protocol. We introduce different LLDN (low latency deterministic network) superframe configurations that show trade-offs among various network parameters. It gives an insight of relationship among various network parameters like sensors refresh rate, number of devices accommodated in network and data payload exchanged between coordinator and end devices with emphasis on different levels of security incorporated.

Low-Latency Distance Protective Relay on FPGA

Abstract: The need for high-speed multi-function protective relays in both traditional transmission systems and the new emerging paradigm of the smart grid is growing. As a widely used protective scheme for transmission lines, a distance relay's high speed and reliable operation to clear faults is essential. This paper proposes a real-time low-latency hardware digital distance protective relay on the field programmable gate array (FPGA). Taking advantage of inherent hard-wired architecture of the FPGA, the proposed hardware distance relay design is paralleled and fully pipelined to achieve low latencies in various relay modules which are developed in textual VHDL language. This low-latency feature allows fast operating and data throughput so that the relay can handle high-frequency sampled data and reach higher computational efficiency. In addition, the parallelism and hardwired architecture of the FPGA makes the design more reliable in computation than the sequential software-based numeric relay. The FPGA-based distance relay can operate on both phasor-based signals and instantaneous signals with 2.09 μs and 0.35 μs latency respectively based on the clock frequency of 100 MHz. The hardware relay is tested in real-time by feeding it with generated faulted current and voltage data for typical faults and the relay response recorded. The results demonstrate the speed and effectiveness of the hardware distance relay.

A low-latency and high-throughput scheduler for emergency and wireless networks

Abstract: Providing QoS guarantees, boosting throughput and saving energy over wireless links is a challenging task, especially in emergency networks, where all of these features are crucial during a disaster event. A common solution is using a single, integrated scheduler that deals both with the QoS guarantees and the wireless link issues. Unfortunately, such an approach is not flexible and does not allow any of the existing high-quality schedulers for wired links to be used without modifications. We address these issues through a modular architecture which permits the use of existing packet schedulers for wired links over wireless links, as they are, and at the same time allows the flexibility to adapt to different channel conditions. We validate the effectiveness of our modular architecture by showing, through formal analysis as well as experimental results, that this architecture enables us to get a new scheduler with the following features, by just combining existing schedulers: execution time and energy consumption close to that of just a Deficit Round Robin, accurate fairness and low latency, possibility to set the desired trade-off between throughput-boosting level and granularity of service guarantees, by changing one parameter. In particular, we show that this scheduler, which we named Highth-roughput Twin Fair scheduler (HFS), outperforms one of the most accurate and efficient integrated schedulers available in the literature.

Dynamically adjusting frame mtu to support low-latency communication

Abstract: In one embodiment, a sender in a shared-communication network determines whether a pending frame is low-latency or high-throughput, and sets a maximum transmission unit (MTU) of the pending frame as a first MTU in response to a low- latency frame and a longer second MTU in response to a high-throughput frame. In another embodiment, a receiver receives a data frame from a sender according to an MTU, and determines a trigger for adjusting the MTU based on latency requirements. In response to the trigger, the receiver sets an interrupt flag in a link-layer acknowledgment for the received data frame. In still another embodiment, a sender determines a pending low-latency data frame to send to a receiver operating according to an MTU, and sends a control message to the receiver to indicate the pending low- latency data frame and an adjusted MTU.

SW-MAC: A Low-Latency MAC Protocol with Adaptive Sleeping for Wireless Sensor Networks

Abstract: A low duty-cycle operation medium access control (MAC) protocol is very important to conserve energy for resource-constrained wireless sensor networks. Traditional sleep-wake scheduling mechanisms of MAC protocols either require periodic synchronization beacons or bring high end-to-end delivery latency due to the lack of any synchronization. In this paper, we propose a low latency MAC protocol by adjusting the sleep window (SW-MAC) considering traffic patterns. Nodes in SW-MAC transmit a sequence of scout packets to wake up the next hop and estimate the traffic arrival time from upstream nodes to sleep adaptively. For the large variance traffic, we adjust the sleep window using additive increase/multiplicative decrease mechanism. And then we design a scout-based scheduling mechanism with the above algorithms to shorten the delivery latency. Simulation results indicate that SW-MAC could significantly reduce the end-to-end packet delivery latency without sacrificing energy efficiency.