Showing papers on "Multiplexer published in 1995"

Wireless on-premises video distribution using digital multiplexing

Abstract: A digital network delivers multiplexed channels to a customer premises. Each multiplexed channel contains a digitally multiplexed data stream including digitized broadband information relating to a number of programs. At the customer premise, a shared processing system includes several channel selectors and program selectors. Each channel selector selects one of the multiplexed channels, and each program selector selects digitized broadband information relating to a selected program from a selected channel. A multiplexer combines the selected digitized broadband information from the program selectors into a transport stream. A transmitter system, for example comprising a digital modulator, a spread spectrum modulator and a broadcast antenna, provides a wireless broadcast of the digital transport stream throughout the customer premise and possibly one or more near by premises. Terminal devices within range of the broadcast receive the wireless broadcast and process selected digitized broadband information from the transport stream to present information relating to a selected program, e.g. on an associated television set.

Transmission characteristics of arrayed waveguide N/spl times/N wavelength multiplexer

Abstract: To realize practical wavelength division multiplexing (WDM) systems, a high-performance N/spl times/N wavelength multiplexer is introduced that is based on an arrayed-waveguide grating. Its transmission characteristics are theoretically derived and experimentally confirmed. A prototype is constructed using the previously proposed techniques that attain low insertion loss and polarization independent operation. It has 16 channels (N=16) with a spacing of 0.8 mn, or 100 GHz, in the 1.55-/spl mu/m band. Frequency relation between input and output ports, free spectral range, and passband width are determined. A demonstration of IM-DD pulse transmission shows that there is no degradation of bit error rate resulting from the finite passband width and crosstalk of the multiplexer. It is confirmed that the multiplexer can realize highly reliable N-channel WDM and WDM-based N/spl times/N interconnect optical networks. >

Polarization-independent all-fiber wavelength-division multiplexer based on a Sagnac interferometer.

Abstract: An all-fiber wavelength-division multiplexer (WDM) based on the nonreciprocity of the birefringence to the polarization states is proposed. The transfer function of a Sagnac interferometer is wavelength dependent if the loop birefringence of the interferometer consists of both circular and linear parts. Theoretical analysis shows that the output characteristics of this WDM are similar to those of a fiber taper-based device. Both the bandwidth and the peak wavelength of the new WDM can be tuned by changing the loop birefringence. Experimental prototypes exhibit a channel isolation greater than 25 dB with peak passband insertion loss of less than 1 dB.

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

Coarse-grained look-up table architecture

Abstract: A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection resources include switch boxes (310), long lines (340 and 350), double lines (360 and 370), single lines (385), and half- (330) and partially populated (320) multiplexer regions. The LAB includes two levels of function blocks. In a first level, there are eight four-input function blocks (601). In a second level, there are two four-input function blocks (670) and four secondary two-input function blocks (672). In one embodiment, these function blocks are implemented using look-up tables (LUTs). The LAB has combinatorial and registered outputs. The LAB also contains storage blocks (691) for implementing sequential or registered logic functions. The LAB has a carry chain for implementing logic functions requiring carry bits. The LAB may also be configured to implement a random access memory.

Capacitive touch detectors

Abstract: A capacitive touch detector comprises means to improve selectivity - a narrow band buffer. Means for reducing the effect of noise comprise capacitive coupling of the buffer into the detector, which comprises a plurality of sensor pads of different inherent capacitances and means to approximate impedances which include said capacitances and are adapted to operate at respective frequencies to approximate the impedances. At least two multiplexers are arranged in series to lower capacitance loading of the sensor pads. A synchronous demodulator is arranged to be connected as a tracking filter to track the frequency of a capacitance-measuring signal from one to another of the sensor pads, possibly during a scan thereof. A controller is connected to a number of pads or capacitive sensing zones by way of buffered multiplexer chips and, shielded connectors and cables. The buffered multiplexer chips can be cascaded in series or wired in parallel and are driven from a level translator which can in its simplest form comprise a resistor and capacitor network but should preferably comprise active elements. This ensures that the base voltage on (the voltage first applied in a halfwave to) a sensor pad is also applied to its shield and various parts (e.g. power supply rails, control port, chip substrate) of its associated multiplexer/s. The signals derived from this electronic scanning array are then further processed by a signal processor incorporating a microprocessor. The improvements relate to obtaining and processing the signal both in the analogue and digital domains and allow more reliable touch detection, including interpolation methods.

Method and apparatus for transmitting information recorded on information storage means from a central server to subscribers via a high data rate digital telecommunications network

Abstract: The invention provides a method and apparatus for transmitting information recorded on information storage from a central server via a high data rate digital telecommunications network to subscribers connected to the network. The telecommunications network is capable of two-way communication. The central server includes a central communication interface connected to the network, a magazine containing a very large number of disks, disk players, a controller for transfer of the disks between the magazine and the disk players, a central computer, a memory for storing information relating to the locations of the disks, and a multiplexer. Each of the subscriber stations includes a communication interface connected to the network, a computing terminal, a demultiplexer, a data rate expansion circuit, a digital-to-analog converter, and a transducer for converting analog signals into humanly perceptible signals. In one example, the invention provides for the delivery to a subscriber of a personalized sound program selected from a large directory of available selections.

Arrayed-waveguide grating multiplexer with flat spectral response.

Abstract: The design principle of a single-mode arrayed-waveguide grating multiplexer with flat spectral response is proposed on the basis of a discrete Fourier transform. By a beam propagation-method simulation, a flat spectral region (within 1-dB loss increase) is obtained over 57.2 GHz for 100-GHz channel spacing.

16-channel optical add/drop multiplexer using silica-based arrayed-waveguide gratings

Abstract: An optical add/drop multiplexer (ADM) that enables full access to 16 individual wavelength channels has been fabricated on a planar lightwave circuit (PLC). The device consists of three arrayed-waveguide gratings which are connected by 16 thermo-optic switches. The on-off crosstalk for the main input to the main output port is less than -24 dB and that for the main input to the drop port is about -13 dB. The fibre-to-fibre insertion losses are 7-8 dB and 3-4 dB when signals are coupled to the main input port and to the add port, respectively.< >

Fabrication of 64*64 arrayed-waveguide grating multiplexer on silicon

Abstract: A 64 channel arrayed-waveguide multiplexer with 0.4 nm (50 GHz) channel spacing at 1.55 µm has been fabricated using SiO2/Si waveguides. The authors obtained a crosstalk of less than –27 dB to neighbouring and all other channels. The on-chip insertion loss ranges from 3.1 to 5.7 dB for central and peripheral output ports, respectively.

Method and apparatus for utilizing the available bit rate in a constrained variable bit rate channel

Abstract: A system for utilizing the available bit rate in a constrained variable bit rate channel is described. The system receives one or more encoded information streams, each having a variable bit rate. Rate control circuitry controls the rate of transmission of the encoded information streams so that the variable bit rate of the streams is transformed into a constrained variable bit rate, in which the variable bit rate is limited to a predetermined maximum value. A multiplexer multiplexes the encoded information streams for transmission over a channel. The channel may comprise a 6 MHz television channel. The multiplexer also multiplexes the encoded information streams with a secondary information stream for transmission over the channel. For purposes of multiplexer selection of information streams, the secondary information stream is assigned a lower priority than the encoded information streams. The encoded information streams may, for example, carry video data, whereas the secondary information stream may, for example, carry application data. The multiplexer may select from among the encoded information streams according to a round-robin scheme. The rate of the secondary information stream depends upon the rates of the encoded information streams. The rate of the secondary information stream may be controlled by a transmission control protocol, where the rate is adjusted by adjusting a transmit window of the protocol.

Power-saving circuit and method for driving liquid crystal display

Abstract: A power-saving column driver integrated circuit, and a power-saving method for driving a liquid crystal display, include a series of multiplexers coupled to the columns of the display. The multiplexers selectively couple each of the columns to a common external storage capacitor during a portion of each row drive period for discharging each of the pixels in the selected row of the liquid crystal display to a median bias voltage. During the remaining portion of each row drive period, the multiplexers selectively couple voltage drivers to the columns of the LCD pixel array for applying a desired driving voltage to each column of the array. The polarity of the driving voltages applied to each column alternates on succeeding row drive periods, and the resulting voltage that is summed on the storage capacitor averages to the median bias voltage. For active matrix liquid crystal display panels, a multiplexer selectively couples the backplane of the display panel to either an external storage capacitor or to an alternating-polarity backplane driving voltage during each row drive period.

Neural semiconductor chip and neural networks incorporated therein

Abstract: A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the "fire" type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. In a multi-chip network, an additional OR function is performed between all corresponding first global result and output signals (which are intermediate signals) to generate second global result (R**) and output (OUT**) signals, preferably by dotting onto an off-chip common communication bus (COM**-BUS) in the chip's driver block (19). This latter bus is shared by all the base neural network chips that are connected to it in order to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the intermediate output or the global output signal to be fed back to all neuron circuits of the neural network, depending on whether the chip is used in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal is the result of a collective processing of all the local output signals.

Cell multiplexer having cell delineation function

Abstract: A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.

Serial communication interface system having programmable microcontroller for use in a battery pack

Abstract: A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry such as a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The microcontroller also includes an I 2 C interface for supporting a bi-directional two wire bus and data transmission protocol that is useful for serially communicating with other peripheral or microcontroller devices. By making use of the I 2 C interface, the microcontroller can be programmed while in the end application circuit. Such a feature allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This allows the most recent firmware or a custom firmware to be programmed.

ASIC bus structure

Abstract: A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer ≧2), coupled in a point-to-point configuration. Each module is associated with an input/output port that can communicate with the bus. Each module has an output port (Dout), and arbitration ("ARB") port, and X input ports ("LOCALout", "Din1", "Din2", . . . "Din[X-1]"). The Dout output port of an M i module is coupled, via a portion of conductive bus, to [X-1] input ports on an adjacent D i+1 module. Thus, module M 0 's Dout 0 output port is coupled to [X-1] input ports on module M 1 , module M 1 's Dout 1 port is coupled to [X-1] input ports of module M 2 , and so forth. The modules are X:1 in that the output port of each module is coupled to a chosen one of that module's X INPUT ports, as determined by the state of an arbitration select signal (ARB) coupled to the module's arbitration port. The state of the arbitration select signals defines a bus signal path between the LOCAL out input port of a module coupled to the bus, and the D in input ports of other modules. Because it is point-to-point, low module current may be used, the width of the metallized bus traces may be reduced, and contention-type overlap damage is minimized.

Burst edo memory device address counter

Abstract: A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

Add-drop optical spectrum-division multiplexer

Abstract: An add-drop optical spectrum-division multiplexer for dropping a drop multiplex from an incoming multiplex signal and for adding an add multiplex into an outgoing multiplex signal. The multiplexer includes a demultiplexing device for separating a number of optical carriers from the incoming multiplex signal and for selecting drop carriers which constitute the drop multiplex as well as through carriers which are to be output as the outgoing multiplex signal. The multiplexer further includes an apparatus for selecting a certain number of add carriers from the total number of carriers of the add multiplex, and a coupling device and wavelength converter for allocating fixed wavelengths to the signals which modulate the through carriers and the add carriers.

Expandable wavelength division multiplexed optical communications systems

Abstract: The present invention provides wavelength division multiplexed optical communication systems configured for expansion with additional optical signal channels. In one embodiment, the WDM system comprises N source lasers for producing N optical signal channels, each channel having a unique wavelength where N is a whole number greater than or equal to 2. An optical multiplexer module having N+x inputs, where x is a whole number greater than or equal to 1, optically communicates with each of the N source lasers. The N+x input ports of the multiplexer are configured such that the N input ports are optically coupled to the N source lasers and the x input ports are supplemental ports not optically coupled to the N source lasers. An optical transmission path optically communicates with the multiplexer for carrying a multiplexed optical signal comprising the N optical signal channels. N optical channel selecting modules are provided, each selecting module including a Bragg grating configured to select a unique optical channel wavelength. An optical splitter module optically communicates with the optical transmission path and the optical channel selecting modules. The optical splitter includes N+y output ports, where y is a whole number greater than or equal to 1. The N+y output ports are configured such that each of the N output ports is optically coupled to one of the N optical channel selecting modules and the y output ports are supplemental ports not optically coupled to the N optical channel selecting modules.

Addressing scheme for control network having remote address request device

Abstract: A method and system is provided for assigning addresses to input/output (I/O) devices in a control network, and for verifying addresses assigned to the I/O devices. The system comprises a logic controller providing memory into which a connectivity map may be programmed. The connectivity map defines a specific expected address for each I/O device in the system. The logic controller further provides an external controller bus and logic for downloading the connectivity map to an I/O bus manager connected to the logic controller via the external controller bus. The I/O bus manager provides logic for assigning the specific addresses to the I/O devices. Network nodes connect the I/O bus manager to I/O cluster units in the system, each network node including a multiplexer for multiplexing output signals from the I/O bus manager and a demultiplexer for demultiplexing input signals from the I/O cluster units, the multiplexing/demultiplexing functions provided by a controller area network (CAN) integrated circuit. Each I/O cluster unit includes a multiplexer for multiplexing input signals from the I/O devices and a demultiplexer for demultiplexing output signals from its associated network node, the multiplexing/demultiplexing functions again provided by a controller area network (CAN) integrated circuit. Each I/O cluster unit provides means for manually requesting address assignments and a visual indication of addresses so assigned. Each I/O cluster unit also provides means to manually reject the address assigned to it by the I/O bus manager if the assigned address is not the expected address for the I/O cluster processor defined in the connectivity map.

Passively aligned holographic wdm

Abstract: A passively aligned optical interconnect is described for use as a wavelenth division multiplexer (WDM) and demultiplexer. The device makes use of silicon waferboard for a low cost interconnect. Computer generated holograms are used to effect the multiplexing/demultiplexing as well as focusing of the beams. In an alternative embodiment, the device is used as a beam splitter for monochromatic light. In yet another embodiment, the device is used to spatially separate the polarization states of light.

Single-chip 1062 Mbaud CMOS transceiver for serial data communication

Abstract: This work implements the media independent functions specified in the emerging ANSI fibre channel standard at 1062.5 Mbaud. Integrated onto a single CMOS chip are: two phase-locked loops (PLL) for clock generation and clock recovery, a selectable 1B or 2B parallel interface with corresponding multiplexer and demultiplexer for parallel-to-serial and serial-to-parallel conversion, word alignment logic for byte synchronization, 8B/l0B coder and decoder, and high-speed differential CMOS PECL drivers and receivers for the serial I/O. The chip measures 3.9/spl times/4.5 mm/sup 2/ with 100 I/O and dissipates 1.2 W at 1062 Mbaud with a 3.6 V supply. This design achieves higher-speed operation than previous CMOS work with similar integration, and lower power dissipation with higher integration than bipolar implementations at comparable speeds.

Programmable function unit as parallel multiplier cell

Abstract: A field programmable gate array (FPGA) includes at least one programmable function unit (PFU) which comprises input lines, output lines, and a look-up table (LUT) for generating various functions in response to a configuration bit stream. A first function is an adder/subtracter in which the first input line provides an add/subtract control signal to a multiplexer coupled to a full-adder. The multiplexer determines whether a data bit or its complement is coupled to the full-adder. A second function is an AND gate coupled to the full-adder in which the first input line provides a data bit to the AND gate. The second function provides a basic cell for a parallel multiplier. Furthermore, the first input line may be used as a control line or a data line for a general logic function, depending on the PFU function.

Modelling prioritized MPEG video using TES and a frame spreading strategy for transmission in ATM networks

Abstract: This paper presents an efficient transmission mechanism, using frame spreading, for variable bitrate (VBR) MPEG compressed video, through an ATM multiplexer, such as a cable head-end. A priority scheme is implemented in a software MPEG encoder which produces a proportionate traffic in both (i.e., high and low) priority partitions for all three frame types (intraframe, predicted and interpolated) used in MPEG. An ATM multiplexer with a pushout buffer scheme is implemented for the study, in order to provide priority scheduling at the multiplexer for the two priority partitions. The multiplexer is fed with VBR MPEG traffic and performance statistics such as the cell loss ratios are studied for various frame spreading scenarios. Two statistical models are developed using TES (transform expand sample) for VBR MPEG video having two levels of priority. The first model is matched with the empirical histogram and autocorrelation function of each frame type (I, P and B). The second model is created with the assumption of a gamma distribution for the number of bits in each frame type. Experiments are conducted using both models and the results are compared.

Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-optic communication links

Abstract: High-speed multiplexers, demultiplexers, frequency dividers, mixers, and amplifiers are key electronic components in high-speed fiber-optic communications systems such as SONET/SDH. In this paper, we present several important digital and analog integrated circuits (IC) which have been developed for use in SONET/SDH 10 Gb/s optical communication links. The circuits have been fabricated in MOSAIC 5E, an advanced silicon bipolar technology (f/sub T/=26 GHz). The resulting chipset which amounts to a total of 10 IC's consists of multiplexers, demultiplexers, a regenerative frequency divider (2:1), a dual output limiting amplifier, and two different types of mixers for clock extraction. Specifically, the design and performance of these IC's and a hybrid clock recovery module are discussed. The high performance and potential low cost of this research chipset show that advanced silicon bipolar circuit technology can play an important role in future multigigabit fiber-optic communication systems. >

Foot measuring apparatus and circuitry to eliminate multiplexes and demultiplexers

Abstract: The invention pertains to an apparatus for measuring a foot's length and width to correspond to a shoe size and a method to eliminate multiplexers and demultiplexers in circuits. The apparatus is a low profile self-contained apparatus comprising a transducing medium, a microcontroller, a reference impedance element, a signal amplifier, an analog to digital conversion circuit, and a display to generate and display foot sizing data. A microcontroller unit is connected directly to the hybrid multiplexing circuit which! contains algorithms which solve a set of linear equations to indirectly determine the electronic image of a foot. The shoe size is then calculated using a sizing algorithm and then displayed on a display which is connected to the output of the microcontroller unit.

8-channel wavelength division multiplexer based on multimode interference couplers

Abstract: An 8-channel wavelength division multiplexer with 2-nm channel spacing at 1546 nm is proposed. The device is based on the self-imaging effect in multimode waveguides, and design analysis is carried out in a material system with refractive index contrast equal to 1.96%. Simulated loss is less than 0.75 dB for all channels, and the -1-dB and -3-dB full width are 0.75 nm and 1.3 nm, respectively. Crosstalk is below -13 dB in a 0.75-nm-wide window at the neighboring channels. Polarizing change corresponds to a wavelength shift of less than 0.1 nm. >

A new generation of integrated electronic noses

Abstract: At Eurosensors VII the authors discussed the feasibility of integrating the UMIST artificial electronic nose. A tentative sensor deposition technique was reported along with the development of an application specific integrated circuit (ASIC) to perform the analogue signal processing. The following paper reports further progress in achieving this goal. The integrated nose employs two ASICs; a current multiplexer and a current amplifier. Current-mode signal processing has been utilized where appropriate. Arrays of conducting organic polymers have been successfully fabricated. Results are presented on the dynamics, reproducibility and matching of the sensing elements.

Fir filter architecture

Abstract: A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C1 -C5) for multiplication with the multiplexed sample and hold circuit output signals (1-5).

System and method for the software emulation of a computer joystick

Abstract: A digital joystick operates in a digital mode or an analog emulation mode In the digital mode, the joystick generates digital data indicating the position of a control stick and the status of buttons and transmits the digital data to the computer The joystick may be coupled to the computer through a game port or a conventional interface port Computer software operating within the computer can receive digital data directly from the joystick if it is operating in the digital mode When in the analog emulation modes the joystick emulates resistances related to the position of the control stick The emulated resistance data emulates the value of corresponding resistances in a conventional joystick The resistance values may be derived from a programmable resistor, a programmable impedance, or a programmable current source Multiplexers may also be used to couple the appropriate resistance value to the conventional game port input