Journal ArticleDOI
A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer
Norio Ohkubo,Suzuki Makoto,T. Shinbo,Toshiaki Yamanaka,Akihiro Shimizu,K. Sasaki,Y. Nakagome +6 more
TLDR
A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology and a new 4-2 compressor and a carry lookahead adder (CLA) have been developed to enhance the speed performance.Abstract:
A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >read more
Citations
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Journal ArticleDOI
Low-power logic styles: CMOS versus pass-transistor logic
R. Zimmermann,Wolfgang Fichtner +1 more
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
Proceedings ArticleDOI
A New Family of High.Performance Parallel Decimal Multipliers
TL;DR: Two novel architectures for parallel decimal multipliers are introduced based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits and three schemes for fast and efficient generation of partial products in parallel are presented.
Journal ArticleDOI
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
Vojin G. Oklobdzija,D. Villeger +1 more
TL;DR: Improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile are discussed, yielding a faster multiplier.
Journal ArticleDOI
A fast parallel multiplier-accumulator using the modified Booth algorithm
TL;DR: A dependence graph (DG) is presented to visualize and describe a merged multiply-accumulate (MAC) hardware that is based on the modified Booth algorithm, in which an accurate delay model for deep submicron CMOS technology is used.
Proceedings ArticleDOI
Low-power 4-2 and 5-2 compressors
TL;DR: This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units, which are building blocks for binary multipliers.
References
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A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
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Conditional-Sum Addition Logic
TL;DR: A comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.
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A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic
Kazuo Yano,Toshiaki Yamanaka,Takashi Nishida,M. Saito,Katsuhiro Shimohigashi,Akihiro Shimizu +5 more
TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Journal ArticleDOI
Carry-Select Adder
TL;DR: The adder system described increases the speed of the addition process by reducing the carry-propagation time to the minimum commensurate with economical circuit design.