Showing papers on "p–n junction published in 1990"

Characterization of p‐type ZnSe

Abstract: Lithium‐doped ZnSe has been grown on (100) GaAs by molecular beam epitaxy. The epitaxial layers are p‐type with net acceptor concentrations (NA−ND) as high as 8×1016 cm−3— the highest ever reported for molecular beam epitaxial ZnSe. Room temperature ac measurements show resistivities as low as 2.9 Ω cm. Higher Li concentrations give rise to self‐compensation and a decrease in NA−ND. The details of the electrical and optical characterization of these layers are presented. Rudimentary blue light emitting pn junction diodes have been fabricated. While these devices show dominant blue emission (463 nm) at room temperature, large turn‐on voltages indicate that the p‐ZnSe/p‐GaAs interface presents a large barrier to hole transport. Moreover, we find that difficulty in making device‐quality ohmic contacts to p‐ZnSe is the next major obstacle to the fabrication of efficient blue light emitting diodes.

Complex opto-isolator with improved stand-off voltage stability

Abstract: Improved resistance to electrical instability of opto-isolators subjected to large stand-off voltages is obtained by coating the semiconductor light sensing element with a high resistivity layer of amorphous silicon while leaving most of the surface PN junction perimeter and nearby regions free of metal. The amorphous silicon prevents mobile ions in the encapsulation, which are driven to the detector surface by the stand-off voltage, from inverting or modulating the conductivity of the detector surface and causing instability. The amorphous silicon also makes it possible to leave most of the light sensitive PN junctions and nearby regions free of metal, thereby simplifying design of complex IC detector chips and increasing sensitivity.

Flat doping profile double-drift silicon IMPATT for reliable CW high-power high-efficiency generation in the 94-GHz window

Abstract: The main results of a theoretical and experimental study of the optimization of flat doping profile double-drift silicon IMPATT diodes for the realization of reliable CW high-power high-efficiency solid-state oscillators operating in the 94 GHz atmospheric propagation window are presented. This study has been carried out by means of an IMPATT oscillator model which takes into account the thermal limitation, bias effect, and diode impedance matching. It relies on an accurate p-n junction device drift-diffusion model that includes the heavily doped regions of the collectors. This model has been used to quantify the influence of the various parameters determining the oscillator RF output performance. An explanation of the interesting noise performance of these millimeter-wave IMPATT diodes is proposed. >

Observation of avalanche propagation by multiplication assisted diffusion in p-n junctions

Abstract: We have investigated for the first time the propagation of the avalanche multiplication over the area of p‐n junctions reverse biased above the breakdown voltage. The multiplication process spreads from the point where the avalanche is triggered to the whole junction area with a speed proportional to the final steady‐state value of the avalanche current. The values of the propagation speed suggest that the phenomenon is due to diffusion of carriers assisted by avalanche multiplication. This effect strongly affects the rise of the avalanche current and turns out to limit the performance of single photon avalanche diodes.

Characterization of SiGe/Si heterostructures formed by Ge+ and C+ implantation

Abstract: Formation of SiGe/Si heterostructures by germanium ion implantation was investigated. A germanium‐implanted layer was grown epitaxially in the solid phase by thermal annealing. Two kinds of crystalline defects were observed. One is a misfit dislocation, and the other is a residual dislocation caused by ion bombardment. The p‐n junction formed in the SiGe layer has a leakage current three orders of magnitude larger than that of a pure Si p‐n junction fabricated with an identical process except for the Ge+ implantation. Carbon doping in the SiGe layer improves its crystalline quality and the junction characteristics.

Silicon avalanche photodiode array

Abstract: A wafer of neutron transmutation doped silicon having a pn junction between extended opposite surfaces is formed with bevelled edges. A plurality of reverse biased signal contacts is disposed on one surface to provide an integrated array of avalanche photodiodes.

Ultrashallow, high doping of boron using molecular layer doping

Abstract: A new doping method named molecular layer doping (MLD) is proposed. MLD is based on surface chemical adsorption of dissolvements from induced dopant gas molecules. Ultrashallow boron‐doped layers are successfully achieved by MLD using B2 H6 gas. The p+ n junction formed by MLD exhibits excellent characteristics, with a reverse bias leakage current of less than 2.5×10−16 A/μm2 at 5 V. MLD is attractive in that it offers high‐density, shallow‐junction, damage‐free, selective doping in a short time.

Process for anisotropic etching of silicon plates

Abstract: Electrochemical etching of silicon wafers or plates, on the front side of which a monocrystalline epitaxy layer is provided having a doping of a type opposite to the doping of the remainder of the silicon plate, so as to provide a pn or np junction, is performed with an organic photo film material of negative type and polyisoprene base serving as a passivating layer on the previously etched and metallized front (epitaxy) side. The film layer is held in place with the help of an adhesion promoting silane compound and covers the entire front side including the portions previously masked with silicon nitride or oxide. It is dried and hardened before exposure to the etchant which is used to etch the rear side of the plate until the etchant reaches the pn junction, where a small voltage bias applied to the junction from the front side assures an etch-stop. Etchants containing tetraalkylammonium hydroxide in water solution or in water-free form are preferred, with various additives as inhibitors, complexing agents and/or wetting agents.

Polarization- and wavelength-insensitive guided-wave optical switch with semiconductor Y junction

Abstract: A polarization- and wavelength-insensitive semiconductor guided-wave optical switch with a Y junction is proposed. The switch exhibits a digital response with respect to current, allowing its use as a wavelength-insensitive 1*2 optical switch. The switching characteristics are analyzed by using the beam propagation method, and a design example is given. The polarization- and wavelength-insensitive switching operation has been confirmed with a fabricated GaAs/GaAlAs switch at wavelengths of 1.3 and 1.55 mu m, and the on/off ratio exceeded 20 dB at an injection current of 250 mA at these wavelengths. >

Compound semiconductor light emitting element

Abstract: PURPOSE: To enable the accurate control of the semiconductor properties including electric properties and optical properties and get a blue light emitting diode with high brightness, wherein element properties are improved sharply, by sharply reducing the degree of unconformity of lattice in the element of conventionalGaN/αAl 2 O 3 orGaN/AlN/α- -Al 2 O 3 structure, by the GaN/ZnO structure which becomes the primary combination in the structure of a light emitting element. CONSTITUTION: An ZnS 1- XOX epitaxial shock absorbing layer (ntype) 2, a ZnO layer (n-type) 3, a GaN epitacial layer (n-type) 4, a GaN epitaxial layer (p-type) 5, and an Al positive electrode 6 are provided on an ZnS(111) substrate 1, and 7 is an Al negative electrode. The GaN pn junction light emitting element constituted this way operates as a light emitting diode by voltage being applied between electrodes 6 and 7, and under the condition of 3V in rising voltage and 10mA in the current at application of 3,5V voltage, it shows 480nm light emission peak wave length, and 30mcd in light emission brightness. COPYRIGHT: (C)1992,JPO&Japio

Method of producing field effect transistor

Abstract: An impurity adsorption layer is selectively formed from a gas containing an impurity on a semiconductor surface. Solid-phase diffusion of the impurity is effected from the impurity adsorption layer into the semiconductor surface to form a source region and a drain region having a sufficiently small resistivity and an ultrashallow PN junction depth, thereby producing a metal-insulator semiconductor field-effect-transistor featuring fast operating speed and reduced dimensions.

Semiconductor structure with closely coupled substrate temperature sense element

Abstract: MOSFET devices (82) or circuits (80) incorporating an improved substrate temperature sensing element (94) are obtained by forming a PN junction (J2) directly on a thin (gate) dielectric region (140). The temperature sense junction (J2) is desirably formed in a poly layer( 134). By mounting it directly on thin (gate) dielectric (140) its thermal response to temperature changes in the substrate (111) is improved while still being electrically isolated from the substrate (111). It is desirable to provide over-voltage protection elements (100) coupled to the junction (J2) to avoid rupture of the underlying thin dielectric (140). Because the sense diode (94) and all the over-voltage protection devices (102) may be made of poly (136,138,144) with junctions (J2) perpendicular to the substrate (111), the structure is particularly compact and simple to fabricate.

Ion-implanted Si pn-junction detectors with ultrathin windows

Abstract: Nuclear radiation detectors have been fabricated by using ion implantation and the Si planar processing technology. While ion dose and energy were kept constant at values of 5 × 10 14 B/cm 2 at 12.5 keV and 2.5 × 10 15 P/cm 2 at 30 keV, the annealing temperature has been varied between 500 and 1000°C. The Si p + -n dead layer, or detector window, has been measured as a function of the annealing state by using the technique of tilting the detector surface with respect to an incident α-particle beam. The resulting energy losses of the monoenergetic particle beam have been measured with standard high-resolution nuclear spectrometric techniques. The result is that annealing beyond 800°C is necessary to reduce the window thickness from about 0.2 μm to well below 0.1 μm, the concomitant deterioration in detector current being negligible.

Scanning tunneling spectroscopy on cleaved silicon pn junctions

Abstract: Scanning tunneling microscope (STM) I–V experiments in air on freshly cleaved Si pn junctions, are presented. It is shown that the interaction between the tip and the sample may cause the whole structure to behave as a solid‐state device. With the tip in the vicinity of the pn junction the junctions depletion layer may pinch off the tip current, in much the same way as the increasing gate bias of a junction field‐effect transistor reduces the channel current. Under other bias conditions, the STM tip may locally forward bias the pn junction causing a sharp increase in the tip current. Using this mode of operation the pn junction was localized to within 50 nm. A dependence of the tip‐sample I–V characteristic on the local impurity concentration of the sample was also observed. A simple qualitative model consisting of a diode, which represents the tip–Si junction, in series with the resistance of the underlying material, explains these measurements.

Process for manufacturing a high-voltage withstanding planar p-n junction

Abstract: Starting from a planar pn junction (12a, 12b) which isolates a semiconductor region (11a, 11b) of a first conduction type from a semiconductor body (1) of a second conduction type, the peripheral region (11b) of the semiconductor region having a lateral doping gradient over its entire width, which exceeds the penetration depth of the semiconductor region, a part of the peripheral region (11b) is removed in an etching step. The etching depth (17) is so dimensioned that the surface breakdown voltage of the p-n junction (12a, 12b) is adjusted to specified value.

Orientation-dependent doping in organometallic chemical vapor deposition on nonplanar InP substrates: Application to double-heterostructure lasers and lateral p - n junction arrays

Abstract: In this letter we show that the orientation dependence of dopant incorporation can be used to obtain lateral patterning of doping by growing on nonplanar substrates. Specifically, organometallic chemical vapor deposition has been used to obtain lateral p‐n junction arrays and selective deposition of alternating p‐n layers of InP. The latter technique has been used to grow double‐heterostructure lasers with current confinement layers in a single step.

Modelling the inductive behaviour of short-base p-n junction diodes at high forward bias

Abstract: The inductive nature of short-base p - n junction diodes at high forward bias is explained by means of a novel equivalent circuit featuring separate paths for charging currents and convection currents. As suggested by other authors, also conductivity modulation turns out to play a role. The general conclusion is, that the a.c. diode capacitance changes sign when the (modulated) total series resistance of the diode becomes equal to its differential resistance.

Semiconductor substrate structure for use in power ic device

Abstract: A wafer substrate structure has a P type epitaxial wafer layer An N+ type region separation layer is formed on the wafer layer to define a first closed region and a second region neighboring thereto Formed in the first region are a P- type layer and an N- type layer stacked thereon and serving as a high-resistance layer for forming the first element An N- type layer serving as a high-resistance layer exists in the second region of the wafer layer These high-resistance layers are defined by separating a single semiconductor layer by an N+ type diffused separation layer Forming a high-voltage transistor as a power element in the first region to be PN junction-separated brings a "double PN junction separation" structure wherein the first region is electrically separated by a PN junction from the second region and the high-voltage transistor is also PN junction-separated in the first region

Reverse‐bias current reduction in low‐temperature‐annealed silicon pn junctions by ultraclean ion‐implantation technology

Abstract: Reduction in the reverse‐bias current in low‐temperature‐annealed silicon pn junctions has been studied. It has been shown that the transition region existing underneath the ion‐implantation‐generated amorphous layer and the contamination incorporated into this region play a decisive role in determining the reverse current level. In order to minimize the contamination involvement into the transition region, ultraclean ion‐implantation technology has been developed. Ion implantation was carried out under a UHV (5×10−10 Torr) condition in order to minimize the recoil implantation of adsorbed contamination at the surface. The contamination due to the high‐energy ion‐beam sputtering of component parts in the ion implanter has also been suppressed. As a result, a low reverse‐bias current level of about 1.2×10−7 A/cm2 has been obtained for arsenic‐implanted n+p junctions annealed at 550 °C, which is more than two orders of magnitude smaller than that previously reported. The stress compensation technology emplo...

Electrical damage to silicon devices due to reactive ion etching

Abstract: The damage, due to reactive ion etching in CF4+O2 plasma, has been investigated by I-V and C-V techniques using silicon devices such as Au/n-Si Schottky contacts, p+-n diodes and MOS structures. The forward characteristics of a Schottky diode and an exposed junction diode are significantly degraded due to RIE. The amount of damage increases with increasing RF voltage. Considerable recovery occurred when various post RIE treatments were used for the lower RF voltage RIE etching. Almost no recovery upon annealing is found for the higher voltage etching, which suggests the formation of more complex, defect sites at the higher etching voltages. MOS capacitors as well as MOSFETS were used to investigate the damage effects of RIE in Si-SiO2 systems.

A New Mechanism of Failure in Silicon p+/n Junction Induced by Diffusion Barrier Metals

Abstract: The mechanism of failure of p+/n and n+/p junctions under Al-Si/TiN/Ti and Al-Si/ZrN/Zr systems at contact holes has been investigated When the total force of the barrier metal in the metallization system, which is defined as the product of the film stress and the film thickness, is larger than 3×105 dyn/cm, the junction leakage current increases on p+/n diodes, but not on n+/p diodes after annealing at 500°C This increase is caused by the formation of dislocation loops in p+-Si The formation depends on the annealing temperature, the total force of barrier metal and the B concentration

Method of making a high breakdown active device structure with low series resistance

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased inpurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer devices include insulated gate field effect transistors and bipolar devices and the four layer device is a semiconductor controlled rectifier (SCR).

Multiple wavelength p-n junction semiconductor laser with separated waveguides

Abstract: A multiple wavelength semiconductor laser with two active layers separated by either a p-cladding layer or a p-n junction cladding layers A p-disordered region and a n-disordered region extend through one of the active layers and into the intermediate cladding layer A lateral waveguide is formed between the disordered regions in the active layer and a deep waveguide is formed beneath the p-disordered region in the other active layer Since both active layers generate lightwaves at different wavelengths, forward-biasing the p-disordered region can cause either or both waveguides to emit radiation but at different wavelengths The deep waveguide can also be a buried heterostructure laser

Creation of p‐n junction in Hg0.3Cd0.7Te

Abstract: We have used local plastic deformation and electron irradiation to create p‐n junctions in Hg0.3Cd0.7Te. The electron induced current mode of scanning electron microscopy was used to detect the local conversion from p type to n type. Control experiments with CdTe and independent results show that the migration of interstitial mercury and its reaction with an acceptor must be responsible for the observed conversion.

Process for producing a semiconductor device with a bulk-defect region having a nonuniform depth

Abstract: The present invention relates to a semiconductor device e.g., a CMOS, comprising a denuded region and a bulk-defect region, as well as a process for producing, e.g., CMOS. In a conventional CMOS, the distance (dp) between the bulk-defect region and p + -type source or drain region (dp) is greater than the distance (dn) between the bulk-defect region and the p well (dn). As a result, a leakage current can be generated in the PN junction. In order to eliminate the problems caused due to dp>dn, the present invention forms in a semiconductor substrate a bulk-defect region having a depth which is nonuniform in accordance with the nonuniform depth of the semiconductor elements.

Method or producing PN junction device

Abstract: A PN junction device is formed by removing an inert film from a surface of an N type semiconductor layer to expose an active face, then applying a source gas containing an P type impurity component to the active face to form an impurity adsorption film, and thereafter carrying out a solid-phase diffusion of the impurity is carried out from a diffusion source composed of the P type impurity adsorption film into the N type semiconductor layer to form therein a P type semiconductor layer to thereby provide a PN junction. Lastly, a pair of electrodes are connected to the respective semiconductor layers to form the an PN junction device.

Heterostructure p‐n junction tunnel diodes

Abstract: Heterostructure p‐n junction tunnel diodes with high peak to valley ratios (12: 1) at room temperature are demonstrated. The variation of peak and valley currents in diodes with different tunnel barriers is described, and the mechanisms responsible for the valley current and its temperature dependence are proposed. Ways to improve the peak to valley ratio and reduce junction capacitance are discussed.

Field effect transistor using silicon carbide and its manufacturing method

Abstract: PURPOSE: To enable withstand voltage to be increased and on resistance to be reduced by allowing a first junction which is formed between a channel formation layer and a source region to have a different characteristic from that of a second junction which is formed between the channel formation layer and a drain region. CONSTITUTION: A p-SiC single-crystal layer 11 which is a channel-formation layer and a drain region 15 form a pn junction and the p-SiC single-crystal layer 11 which is a channel-formation layer and a source region 16 form a pn junction. Finally, after aluminum A1 is vacuum-deposited as a wiring material, patterning is made for forming wiring electrodes 17 and 18, thus obtaining an n-channel inversion-type MOSFET. Thus, while the pn junction at the source region shows an improved forward characteristic, the pn junction at the drain region shows an improved backward characteristic, thus enabling leak current to be reduced and on resistance to be also reduced. COPYRIGHT: (C)1992,JPO&Japio

Optical amplifier having gain at two separated wavelengths

Abstract: An optical amplifier with a semiconductor body comprising a layer structure grown on a substrate 1 with an active layer 4 situated between two cladding layers (2, 3) with a strip-shaped amplification region bounded by two end surfaces (7, 8) which form the input and output surfaces of the radiation to be amplified. The active layer comprises a number of quantum well (QW) layers 4A with direct band transition, which are separated by barrier layers 4B of a different semiconductor material. The material, the number, and the thickness of the QW layers 4A and the barrier layers 4B in combination with the length 1 of the amplification region are chosen in such a way that two optical transitions can take place in the active layer 4, maximum amplification occurring at a certain current density through the PN junction for the radiation wavelengths corresponding to these optical transitions, while the end surfaces (7, 8) are provided with an anti-reflection layer 9 which has a reflection coefficient R of at most 0.5% for these two wavelengths. An anti-reflection layer made up of four layers of alternately titanium oxide and aluminum oxide is advantageously used.