Showing papers on "Parasitic element published in 1994"

Extracting small-signal model parameters of silicon MOSFET transistors

Abstract: A novel approach to the extraction of small signal model parameters for silicon MOSFETs is described. This technique was developed to extract a high frequency model based only on S-parameter measurements to obtain both the intrinsic and parasitic resistance model parameter values of a small signal model. >

Modelling iron-powder inductors at high frequencies

Abstract: A high-frequency model of iron-powder core inductors is studied. The skin and proximity effects that cause the winding parasitic resistance to increase with the operating frequency are considered. The inductor self-resonance due to the parasitic capacitances is also taken into account. The frequency response of the inductor model is compared to that of an experimentally tested iron-powder core inductor. The first self-resonant frequency is determined from the plot of the measured reactance and allows for the calculation of the parasitic capacitance. Equations for the inductor parasitic resistance are derived in a closed form. Expressions giving the AC resistance as a function of the operating frequency are given. These expressions allow for an accurate prediction of the inductor power loss over a wide frequency range. The measured and calculated values of the inductor impedance magnitude end phase, the real and imaginary parts of the inductor impedance, the inductance, and the inductor quality factor are plotted versus frequency and compared. Theoretical results were in good agreement with those experimentally measured. Therefore, it is demonstrated that the discussed equivalent circuit has a frequency response matching that of the real inductor. Moreover, the circuit model is simple, it allows for an immediate understanding of iron-powder core inductor behavior and can be easily used in computer simulations of electronic circuits. >

Phase-Locked Oscillator Optimization for Arrays of Josephson Junctions

Abstract: An overview of phase locking in two‐dimensional (2D) arrays of identical Josephson junctions is presented. General design criteria are discussed for optimization of power and linewidth. A harmonic balance technique is used to derive an analytic expression for the fundamental power as a function of bias voltage for a single shunted tunnel junction with an external shunt resistor having parasitic inductance. A linear stability analysis is performed on the in‐phase state of 2D arrays in the absence of any external load. Most excitation modes in the 2D array are damped, leading to stable phase locking between parallel junctions within each row; however, within the theoretical model, no mechanisms intrinsic to the array were found to induce phase locking between rows of junctions. The results of these calculations and their impact on and relevance to the design of phase‐locked Josephson oscillators are discussed.

Method of fabricating a semiconductor device with a capacitor structure having increased capacitance

Abstract: A semiconductor integrated circuit device with a capacitor structure having a large capacitance per unit surface is disclosed, wherein a contact hole is formed in an insulator layer, a metal electrode with or without a rugged surface is formed in the contact hole by an ion beam vapor deposition of metal, and a capacitor insulator layer is formed on a surface of the metal electrode The metal electrode is integral with a contact metal The capacitor structure comprises the metal electrode integral with the contact metal and the capacitor insulator layer which are buried in the contact hole The device is improved in planarization, reduction of parasitic resistance, maintenance of capacitance and mass production ability

Composite second-generation current conveyor with reduced parasitic resistance

Abstract: A composite second-generation current conveyor (CCII) with positive or negative current transfer, implemented from two identical CCII/sup +/s having the same value for their bias currents, is described. The parasitic output resistance which appears on port X is considerably reduced from this implementation, without increase of the power consumption. SPICE simulation results using the CCII/sup +/ in its translinear form and implemented from bipolar transistors are given. They confirm the theoretical approach and underline the possibility of the implementation. This is revealed to be more efficient than existing approaches, principally either with low values for the bias current or a low value for the load connected at X.

1.1 GHz oscillator using bondwire inductance

Abstract: Using the parasitic inductance usually associated with a bondwire in an IC package, a bipolar GHz LC-tuned oscillator is designed. Bondwires have very low series resistance and are thus suitable for high-Q applications. Measured results indicate very low phase noise and low power consumption.

0.1 /spl mu/m Schottky-collector AlAs/GaAs resonant tunneling diodes

Abstract: The Schottky-collector resonant tunneling diode (RTD) is an RTD with the normal N+ collector and ohmic contact replaced by a Schottky contact, thereby eliminating the associated parasitic resistance. With submicron Schottky contact dimensions, the remaining components of the parasitic series resistance can be greatly reduced, resulting in an increased maximum frequency of oscillation, f/sub max/. AlAs/GaAs Schottky-collector RTDs were fabricated using 0.1 /spl mu/m T-gate technology developed for high electron mobility transistors. From their measured dc and microwave parameters, and including the effect of the quantum well lifetime, f/sub max/=900 GHz is computed. >

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

Abstract: A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action By reductions in drain electric field and parasitic resistance at a source n/sup -/ region, the BVds was improved with almost the same current drivability as that in single drain structure The behavior of the BVds on LDD n/sup -/ concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n/sup -/ region, which forms the current path, was relaxed effectively at an optimum n/sup -/ doping condition >

Power supply wiring for semiconductor device

Abstract: Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed. The size of the capacitor is half in length as large as the width of the power supply wiring, and the width substantially equals the length of the power supply wiring, the parasitic resistance generated at the gate or inversion layer is suppressed small, and the gate capacitance approximately corresponding to the area of master power supply wiring is interposed between the power source and the ground. As a result, a large capacitance bypass capacitor can be formed between the power source and the ground, and a power supply wiring which is great in effect of eliminating power supply noise can be obtained.

Semiconductor circuit device capable of reducing influence of a parasitic capacitor

Abstract: In a semiconductor circuit device comprising a differential amplifier circuit, which is formed on a semiconductor substrate and which comprises first and second input terminals, and a circuit element formed on the semiconductor substrate and connected to one of the first and the second input terminals. A dummy circuit element is formed on the semiconductor substrate so as to adjoin the circuit element for forming between the dummy circuit element and the semiconductor substrate a dummy parasitic capacitor which is equivalent to a parasitic capacitor formed between the circuit element and the semiconductor substrate. The dummy circuit element is connected to another one of the first and the second input terminals.

Semiconductor integrated circuit device

Abstract: PURPOSE:To prevent the malfunctions of a semiconductor integrated circuit IC device that are caused by the voltage variance and the superposed noises produced on a power line by actuating the logic circuit contained in the IC device with the power voltage stabilized by a built-in constant voltage circuit. CONSTITUTION:An IC device 1 is mounted on a printed circuit board 2 together with other equivalent devices and can externally work with the power voltage Vc1 supplied from an external power supply 3 via a power line 21 with no application of the stabilizing processing. In the device 1, the voltage Vc1 is stabilized to the voltage Vc2 of a fixed level (3V) by a constant voltage circuit 15 and supplied to the circuits 11-13 as the actuating power voltage. Thus it is possible to stably actuate an internal circuit with the voltage Vc2 even though the voltage drop and the superposed noises are caused on the line 21 by the parasitic resistance and the parasitic inductance.

Output driver circuit for restraining generation of noise and semiconductor memory device utilizing such circuit

Abstract: An improved output driver circuit for a semiconductor integrated circuit device, wherein a stepped control voltage generation circuit is connected to the gate of a driving transistor for driving an output terminal DQ. The stepped control voltage generation circuit responds to an applied input data signal to provide a stepped control voltage changing in a stepped form including a plurality of steps to the gate of the driving transistor. The driving transistor therefore changes its state on a step by step basis from a cut off state to a conduction state. Thus, sharp change in output current flowing through the output terminal can be prevented, and noise caused by a parasitic inductance can be avoided, thus preventing an erroneous operation in the device.

Parasitic capacitance cancellation circuit

Abstract: A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

High frequency MOS device

Abstract: A high frequency power MOS device (90) that is built by MOS technology having high speed switching capability. The device provides improved turn-on and turn-off capabilities by providing gate interconnects comprising substantially metallization, thereby reducing parasitic resistance and capacitance. The device may be fabricated by a MOS process relying upon a dual metallization layer (127, 133) for forming the interconnects. The dual metallization layer has substantially less resistivity than the conventional polysilicon and metallization layer interconnect.

Electron Beam Lithography for the Fabrication of Air-bridged, Submicron Schottky Collectors

Abstract: T‐gate technology as is commonly used for field‐effect transistors and high electron mobility transistors has been adapted for use in Schottky‐collector resonant tunneling diodes (SRTDs) devices in which it is necessary for the footprint to be extremely small in both dimensions. By air bridging the contact, GaAs‐based RTDs with projected cutoff frequencies of nearly 1 THz have been fabricated. The process is advantageous for the fabrication of terahertz diodes because of the large periphery to area ratio associated with the small footprint (which reduces the parasitic resistance), because small areas provide better impedances, and because the air bridge both reduces parasitic capacitances and provides certain processing advantages. The process is also inherently planar in contrast with other diode implementations for use at submillimeter wave frequencies. In addition to the GaAs‐based RTDs, the process is also being used for the fabrication of GaAs Mott diodes, which have cutoff frequencies of 12.5 THz and InGaAs/AlAs RTDs, which appear to have cutoff frequencies of 2.5–3 THz.

Connection structure of power element to snubber element and their mounting structure

Abstract: PURPOSE:To enhance the surge-voltage absorption effect of a snubber element in the connection structure of a power element to the snubber element and to enhance a heat-dissipating property in the mounting structure of the power element and the snubber element. CONSTITUTION:Snubber elements and power elements which have been installed respectively on two metal boards 32, 22 are connected electrically at shortest distances via pads 35, 28. Thereby, a parasitic inductance due to interconnections is reduced, and the generation of a radio-wave noise to the outside is reduced. In addition, the integrated and coupled object of both metal boards 22, 32 is inserted into, and mounted on, a groove formed in a heat-dissipating device. Thereby, heat which is generated in the snubber elements is dissipated effectively, and the large shielding effect of the radio-wave noise is obtained.

Pre-regulator with light switch to limit voltage ringing on turn-off

Abstract: A power integrated circuit pre-regulator AC/DC converter circuit which employs a slow turn-off lateral insulated gate bipolar transistor (LIGBT) device as the switching transistor so as to reduce the decay time of a current generated by the parasitic inductance in the circuit upon turn-off of the LIGBT device, thereby to substantially reduce the level of a ringing voltage produced at the drain of the LIGBT device.

Semiconductor device having a circuit for protecting the device from electrostatic discharge

Abstract: A semiconductor device is disclosed which has an input terminal, an input protective device, a first stage circuit connected between the input terminal and an internal circuit, and a ground line system including a plurality of ground lines divided for noise suppression. Ground nodes of the protective circuit and the first stage circuit are connected with each other and to a common first ground line, while the ground nodes of the internal circuit are connected to second and third ground lines. The parasitic resistance formed between the ground nodes for the protective device and for the first stage circuit is reduced, thereby providing a surge voltage not higher than a clamp voltage of the protective device to protect the first stage circuit against electrostatic discharge-induced failure.

Semiconductor device having an output buffer which reduces signal degradation due to leakage of current

Abstract: To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump to continuously boost the input of an NMOS output circuit so long as the output circuit is providing a logic high output signal. The NMOS output circuit has an input for receiving an input signal and an output for driving at least one output signal line. An oscillation circuit provides an oscillating digital signal to the boosting current pump. The pump responds to the oscillating digital signal and to the input signal being in one of two predetermined states to provide additional current at the input of the NMOS output circuit to compensate for the leakage current.

Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET

Abstract: Reduction of source and drain parasitic resistance is quite important in scaled-down MOSFETs as channel conductance increases. In particular, extension areas in the source/drain should be focused upon for 0.25 /spl mu/m and below geometry MOSFETs, taking account of salicide application and realization of extremely shallow junctions. However, an accurate evaluation of parasitic resistance of an extension area has not been established since the resistance is dependent upon gate voltage. Therefore, it has been difficult to indicate a design guideline for the extension area, which is the critical issue in achieving high performance scaled MOSFETs. In this paper, a simple method of measuring parasitic resistance which is applicable to the extension area is proposed. By the proposed measurement, spreading resistance and accumulation resistance were accurately evaluated. As a result, an universal drivability-parasitic resistance curve was obtained. Moreover, a design guideline for the extension area on the source/drain has been proposed, based upon the relationship between parasitic resistance and junction depth. >

Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications

Abstract: Ion-implanted enhancement-mode GaAs MESFET's with an advanced Lightly Doped Drain (LDD) structure have been developed for low cost, low consumption power, and low noise applications. The advanced LDD structure, which consists of step graded (n/sup +/, n', n") source/drain implanted regions and surrounding p-layers located within the n/sup +/-layers, is effective to suppress the short channel effects and reduce source/drain parasitic resistance without increasing the parasitic capacitance. A manufacturable self-aligned process based on a dummy gate has also been developed for the fabrication of this structure. The 0.3 /spl mu/m devices show a noise figure of less than 1 dB with an associated gain of higher than 9 dB at 6 GHz, even at 1 mW operation. Furthermore, standard deviations of noise figure and associated gain are as small as 0.05 dB (at an average of 0.83 dB) and 0.32 dB (at an average of 8.82 dB), respectively, under a 1 mW operation over a 3 inch /spl Phi/ wafer. >

Semiconductor integrated circuit device and manufacture thereof

Abstract: PURPOSE:To provide a MOS semiconductor integrated circuit device and a manufacture thereof in which an operating speed is fast and the manufacturing process is efficient using a novel gate electrode material. CONSTITUTION:A P-type silicon epitaxial growth layer 5 is formed on a P-type silicon semiconductor substrate 1, and a PMOS element region, an NMOS element region and a bipolar element region are formed on the growth layer 5. Since a polycrystalline SiGe gate electrode 23 having the composition ratio of xGex (1>x>0) is formed in the PMOS element, the rate of activation of impurity is high and the resistivity is low even if the growth is performed at a low temperature. Also, a P-type internal base region 18 of the bipolar element comprises an SiGe epitaxial growth layer of a single crystal. By using the growth layer, the gate electrode 23 and the base region 18 can be simultaneously formed in the same process while the parasitic resistance can be reduced.

Dual directivity antenna

Abstract: PURPOSE: To provide the antenna having a dual directivity in a direction of end fire and integrated with a feeding circuit CONSTITUTION: Each of 1st and 2nd antenna sections A,B has a dipole exciting element 1 and a parasitic element 2 in parallel with the element 1, and they are arranged with a matched end fire direction The exciting elements 1 of each of the antenna sections A, B are fed in an opposite phase to each other by a feeding circuit 4 and the directivity of each of the antenna sections A, B is opposite to each other thereby obtaining the dual directivity The dipole exciting element 1 and the parasitic element 2 are printed on a printed circuit board 3 and a couple of elements 1a, 1b of the dipole exciting element 1 extended in the opposite directions are provided to a front side and a rear side of the printed circuit board and the elements 1a, 1b on the opposite sides to each other in the antenna sections A, B are fed in an opposite phase COPYRIGHT: (C)1995,JPO

Variable polarization antenna

Abstract: PURPOSE: To provide a plane antenna appropriate for receiving satellite broadcasting by a circularly polarized wave by arranging a parasitic element having a sufficiently narrow gap as compared with radiation wavelength on a part of it on the front face of a loop-like antenna element at a sufficiently narrow interval as compared with the radiation wavelength. CONSTITUTION: When high frequency power applied to a coaxial contact plug 3 is inputted to an excited element 1 through a feeder line 4, a high frequency current is distributed to the element 1 and an induced current is generated in a parasitic element 5 by the distributed current. Respective values are selected so that the circumferential length of the element 1 is one wavelength of a radiated wave, an interval between a face including the element 1 and a reflector 2 is 0.0667 wavelength, the circumferential length of the element 5 including the length of a gap 6 is 1.25 wavelength, and the width of the gap 6 on the element 5 is 0.025 wavelength. When an angle ϕ p , formed by the X axis and the center of the gap 6 of the element is changed, an angle ϕ p capable of obtaining an excellent axial ratio exists and linearly polarized wave is transformed to a circularly polarized wave. COPYRIGHT: (C)1995,JPO

Semiconductor laser and optical transmission device

Abstract: PURPOSE:To provide a semiconductor laser of a constitution, wherein a parasitic inductance due to the length of a bonding wire between an element electrode on a semiconductor laser element and an external electrode is reduced. CONSTITUTION:A subcarrier 4 is placed on the bottom on the inside of an L-shaped heat sink 6, a semiconductor laser element 1 is fixed thereon, an upper surface electrode 3 on the element 1 is arranged so as to form an angle of about 90 deg. or smaller with the side surface, which is used as an external electrode, on the L-type inside of the sink 6 and the length of a bonding wire 5 to connect both electrodes 3 and 13 to each other is formed so as to become short. In a conventional method, the upper surface electrode 3 on the element 1 and the external electrode 13 are installed in such a way that they are positioned on the same plane, but when the electrode 3 is arranged so as to form an angle of about 90 deg. or smaller with the electrode 13 like this invention, the length of the wire 5 to connect both electrodes 3 and 13 to each other can be made short. As a result, a parasitic inductance is reduced and the high- frequency characteristics of the element 1 are significantly improved.

New GaAs-MMIC process technology using low-temperature deposited SrTiO3 thin film capacitors

Abstract: The authors have developed a new GaAs-MMIC process technology using low-temperature deposited SrTiO 3 thin film capacitors which were combined with WSi-gate selfaligned FETs. The SrTiO 3 films were successfully deposited at 200 o C by the RF magnetron sputtering method without degrading the FET characteristics. By integrating these on-chip SrTiO 3 bypass capacitors onto the GaAs IC, the parasitic inductance from the source to ground interconnection was successfully reduced and an enhanced gain characteristic was obtained for a self-biased amplifier circuit

Wiring structure of semiconductor device

Abstract: PURPOSE:To prevent the operation of a parasitic element by forming resistance layers buried into insulator layer sections corresponding to an element region and an isolation region, forming a wiring layer electrically connected to the resistance layers, removing a part of a surface protective layer covering the wiring layer and shaping a ground pad section to a wiring layer section. CONSTITUTION:A P element isolation region 12 is formed to a second conductivity type semiconductor substrate 10, and first conductivity type element regions 11 are formed into the region 12. The surface of the second conductivity type semiconductor substrate 10 is covered with an insulator layer 14, and resistance layers 16 are buried into the insulator layer 14. Wiring layers 17 are completed to insulator layer 14 sections corresponding to the resistance layers 16 and the isolation region 12 through patterning. A part of a surface protective layer 19 covering the wiring layers 17 is removed, thus shaping a ground pad section 18. Accordingly, structure, in which the wiring layers 17 are connected electrically to the isolation region 12 surrounding the element regions 11 through the resistance layers 16, is formed, thus inhibiting the breakdown prevention of reverse connection and parasitic element operation resulting from current fluctuation.

Field effect transistor, and its manufacture

Abstract: PURPOSE: To reduce parasitic resistance to limit variations in characteristics while maintaining high breakdown strength. CONSTITUTION: An nAlGaAs electron supply layer is provided above a GaAs channel layer 12, and a low-resistance nGaAs contact layer (a first semiconductor layer) 14 is provided between source and drain electrodes and an electron supply layer. A high-resistance layer (a second semiconductor layer) 17 is made at the side face of the contact layer and continuously from it between the gate electrode the gate electrode 15 and the contact layer 14. As a film to be made at the sidewall and continuously from it on the electron supply layer, not a conventional insulating film but a semiconductor is used, and besides since the lattice of AlGaAs matches with that of GaAs, and the width of the band is large, the reduction of parasitic resistance and the suppression of variations in characteristics can be made, with high breakdown strength kept. COPYRIGHT: (C)1996,JPO

Field effect transistor and its manufacture

Abstract: PURPOSE:To reduce the gate parasitic capacitance of a field effect transistor and improve the high-frequency characteristic of the transistor. CONSTITUTION:A recess 82 is constituted of a bottom surface 82A, first tapered surface 82B, and second tapered surface 82C and a gate electrode 1 is positioned with the lower end of its support section 1A on the bottom surface 82A. In addition, the lower end of the side wall of the support section 1A is made coincident with the lower edge of the first tapered surface 82B. Therefore, the gate parasitic capacitance and parasitic resistance of this field effect transistor can be reduced.

Method of manufacturing semiconductor device

Abstract: PURPOSE:To make it possible to reduce the parasitic capacitance and parasitic resistance of a MOS-FET by burying a conductive material into a groove extending to an upper side gate insulation film through a lower side gate and an insulation film to lead out source and drain electrodes by means of a conductive material. CONSTITUTION:A field oxide film 32 is formed in the element isolation region, a lower side 2 is formed in an SOI insulation film within the element forming region enclosed in the element isolation region, and an oxide film 31 is formed on it as a lower side gate insulation film. A gate insulation film 6, a poly-silicon film 7 for the upper side gate, a nitride film 8 as a stopper film for the polishing and etching, and an upper layer oxide film 9 are deposited on a substrate. The both sides of the gate is anisotropically etched with a mask 5 and removed. Then, an oxide film 10 is deposited on the whole surface, ion species 11 is implanted, and heat-treatment is performed to form an LDD region 12. Then, the stopper film 8 is exposed by anisotropical-etching, and an SiO2 film 13 is formed on the whole surface of the substrate to fill the groove with a resist 14.