Showing papers on "Parasitic element published in 1999"

Diversity gain from a single-port adaptive antenna using switched parasitic elements illustrated with a wire and monopole prototype

Abstract: A new concept in single-port adaptive antennas using parasitic elements with switched terminating impedances is presented including results from a concept prototype. Each parasitic element can be effectively terminated in three impedance values. The antenna concept provides multiple radiation patterns with a single RF signal port without the need for RF switches or phase shifters in the direct RF signal path. Impedance variations in the active antenna element are minimized by use of only rotationally symmetric configurations. Measured patterns are used to demonstrate the performance improvement expected using switched diversity combining in a simulated uniform scattering scenario. The concept prototype having one active element and four parasitic elements, is shown to have equivalent diversity performance to between three and four uncorrelated branches.

A metal-oxide-semiconductor varactor

Abstract: CMOS technology scaling opens up the possibility of designing variable capacitors based on a metal oxide semiconductor structure with improved tuning range and quality factor. This is due to an increase in the oxide capacitance and a reduction in the parasitic resistance. A prototype metal-oxide-semiconductor (MOS) variable capacitor of 3.1 pF nominal value has been realized in a 0.35-/spl mu/m standard CMOS process. A factor two capacitance change has been achieved for a 2-V variation of the controlling voltage. The varactor Q ranges from 17 to 35, at 1.8 GHz.

Parallel RC current detection circuit and DC/DC converter with a parallel RC current detection circuit

Abstract: An RC series circuit is provided in parallel with an inductor. The RC series circuit is comprised of a resistor and a capacitor which are connected with each other in series. A voltage across the capacitor is applied to a detection circuit. The detection circuit detects inductor current flowing through the inductor based on the applied voltage. If the inductance of the inductor, the parasitic resistance value of the inductor, the capacitance of the capacitor and the resistance value of the resistor are L, RL, C a and R a , respectively, the RC series circuit is designed so as to satisfy L/RL=C a *R a .

High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

Abstract: Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMT's (E-HEMT's) is described for the first time. Most important issue for the fabrication of E-HEMT's is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 /spl Omega//spl middot/mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-/spl mu/m gate E-HEMT's. This is therefore one of the promising devices for ultra-high-speed applications.

Two-dimensional doping profile characterization of MOSFETs by inverse modeling using I-V characteristics in the subthreshold region

Abstract: In this paper, we present a new technique for the characterization of two-dimensional (2-D) doping profiles in deep submicron MOSFETs using current-voltage (I-V) characteristics in the subthreshold region. The main advantages of the technique are as follows. (1) It is capable of extracting 2-D doping profile (including channel-length) of deep submicron devices because of its immunity to parasitic resistance, capacitance, noise, and fringing electric fields. (2) It does not require any special test structures since only subthreshold I-V data are used. (3) It is nondestructive. (4) It has very little dependence on mobility and mobility models. (5) It is easy to use since data collection and preparation are straightforward. (6) It can be extended to the accurate calibration of mobility and mobility models using I-V characteristics at high current levels, because errors associated with uncertainties in doping profiles are removed.

Positive-negative pulse type high frequency switching power supply unit

Abstract: The invention provides a positive-negative type high frequency switching power supply unit which provides a high frequency output of an ideal sine waveform to allow reliable switching with very low switching loss without being influenced by a leakage inductance of the load side, a parasitic capacitance and a parasitic inductance produced by a wiring line or the like, and a load condition. The positive-negative type high frequency switching power supply unit includes an H-bridge switching circuit including four semiconductor switching elements connected in an H-bridge connection, a resonance circuit which resonates with a positive-negative pulse wave outputted from the H-bridge switching circuit, and a PWM control circuit for detecting a voltage and current of the resonance circuit by means of a pulse transformer and a current detector, respectively, and feeding back the voltage and current to the H-bridge switching circuit so that the four semiconductor switching elements may perform switching operations in a switching frequency higher than the resonance frequency of the resonance circuit in a fixed switching pattern of on/off states.

Phased array antenna

Abstract: PROBLEM TO BE SOLVED: To improve performance of an antenna, such as a phased array antenna, that applies to a high frequency body with high gain. SOLUTION: This phased array antenna provided with 12×12 sets of radiation elements is configured by placing 3×3 sets of modules 110 of a multilayer structure each provided with 4×4 radiating elements on the same plane of a distribution layer 120 that is a base. The module 110 is comprised of a parasitic element layer 111, a radiating element layer 112, a phase control layer 113 and a distribution combining layer 114.

Semiconductor integrated circuit

Abstract: In order to prevent variations in a power-supply voltage caused by a parasitic inductance, a series circuit including at least one resistance and at least one capacitance is provided adjacent to a switching circuit, between a high-voltage-side interconnection and a low-voltage-side interconnection of the power-supply voltage for the switching circuit

Suppression of coupled-slotline mode on CPW using air-bridges measured by picosecond photoconductive sampling

Abstract: For the first time, the effect of air-bridges on the suppression of the unwanted coupled-slotline (CSL) mode on a coplanar waveguide (CPW) is experimentally observed up to 250-GHz bandwidth, based on the picosecond photoconductive sampling technique. The CSL mode is initially originated from the asymmetric pulse generation on the CPW using ultrashort laser pulses and photoconductive switches. We find that more than two crossover air-bridges are needed to remove the unwanted CSL modes. The parasitic capacitance for the crossover air-bridge over the CPW and the parasitic inductance for the ground connecting air-bridge along the CPW are crucial in determining the signal distortion.

Line inductance extraction and modeling in a real chip with power grid

Abstract: A realistic power grid and pseudo-random signal lines connected to on-chip drivers are included for accurate extraction of the parasitic inductance in a 5-metal layer 025-/spl mu/m CMOS technology A new ring oscillator for the extraction of signal delay and characteristic impedance is demonstrated The increase of signal delay due to mutual inductance of clock lines is measured directly with S-parameter characterization techniques

Studies of self-driven synchronous rectification in low voltage power conversion

Abstract: In self-driven synchronous rectification circuit, transformer secondary winding is often used directly to drive synchronous MOSFETs. Transformer leakage inductance and other parasitic inductance in the rectification loop are found to contribute to rectification loss. The body diode of synchronous rectifiers is on during current commutation in two SRs because reflected secondary voltage falls on these parasitic inductances instead of the gate terminal of SR in this duration. Body diode turn on greatly degrades the performance of SR. The case is worse in high frequency, high current applications. Detailed analysis of this phenomenon is given in the paper. An equivalent model is established to analyze and evaluate the performance of SR with the existence of parasitic inductance. Simulation and experiment waveforms confirm the model and analysis. Additionally, optimal driving waveforms for SRs are discussed. Two improved gate drive methods are presented and compared.

Non-volatile semiconductor storage device and its manufacture

Abstract: PROBLEM TO BE SOLVED: To reduce both of the junction withstand voltage of a high withstand voltage transistor and the parasitic resistance of a low-voltage transistor by performing the ion implantation of the N plus diffusion layer of the high breakdown voltage transistor from the outside of two types of side walls and from the outside of the first side wall in a low-voltage transistor. SOLUTION: A thin side wall 10 is formed at a memory cell 202 and a low- voltage transistor 204. A second side wall 11 is formed at a high breakdown voltage transistor 203 in addition to the side wall 10. Therefore, since thickness 12 of the side wall is large in the high breakdown voltage transistor 203, a distance 16 from an N plus diffusion layer 207 to the tip of an N minus diffusion layer 206 becomes long. On the other hand, in the low-voltage transistor 204, there is only the first side wall 10, so thickness 14 of the side wall 10 becomes thinner than before for distance 17 between gate electrodes 201 and 212 of the transistor of the memory cell 202 and the low-voltage transistor 204 and a contact hole 210, thus suppressing parasitic resistance.

Parasitic dual band matching of an internal looped dipole antenna

Abstract: An internal, loop dipole antenna for a mobile terminal is capable of operating in two distinct RF bands. The antenna includes a resonating element and a parasitic tuning element. The resonating element has a looped, dipole configuration including a primary tuning loop, a secondary tuning loop, and a ground loop. The parasitic tuning element is disposed in a plane spaced from the plane of the resonating element. The parasitic element includes a first portion that generally follows the ground loop on the resonating element, and a second portion that bisects the primary tuning loop on the resonating element. First and second tuning arms extend along opposing ends of the parasitic tuning element. The length of the tuning arms is adjusted to tune the resonance of the antenna in the primary and secondary operating bands.

Isolation improvement mechanism for dual polarization scanning antennas

Abstract: An antenna arrangement is provide with a variable parasitic element whose position is varied as a function of the scan angle According to an exemplary embodiment of the invention, a variable scanning array dual polarized antenna provides different scan angles by varying phase elements of the array According to this embodiment an adjustable phase shift mechanism is used to modify the phase of the antenna array The adjustable phase shift mechanism is used changes the antenna's phase as a function of a moveable dielectric slab The dielectric slab slides over a microstrip line that results in a phase change that is a function of line coverage A parasitic element is also connected to the dielectric slab such that the position of the parasitic element is varied in response to a change in the phase shift mechanism thereby varying the canceling signal of the parasitic element to optimize port isolation for the dual polarized antenna

Switched parasitic feeds for parabolic antenna angle diversity

Abstract: The radiation direction from a parabolic dish antenna can be electronically controlled through the use of a switched parasitic element closely coupled to a dipole feed. Through the application of a dc voltage, the half-wavelength-long parasitic element is switched between open and short circuit using a p-i-n diode at its center. With a parasitic element vertically offset from the horizontal dipole, the performance of the antenna in both switch positions has been optimized. At 1.5 GHz, using a 2.4 m diameter reflector, beam skewing on the order of 1.5° at the −6 dB point can be achieved for a feed element spacing of 0.6 wavelengths. At a parasitic element spacing of 0.5 wavelengths, the main lobe is better than 15 dB above the unshifted null. The analysis of such a structure requires the calculation of the current in both the driven element and the parasitic element and the summation of their fields on the surface of the reflector independently. ©1999 John Wiley & Sons, Inc. Microwave Opt Technol Lett 23: 200–203, 1999.

SiGe HBTs and ICs for optical-fiber communication systems

Abstract: An ultra-high-speed selective-epitaxial-growth (SEG) SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes has been developed. A 0.54-μm-wide SiGe base self-aligned to the 0.14-μm-wide emitter, which reduces collector capacitance, was selectively grown by using a UHV/CVD system. SMI electrode technology, which enables low parasitic resistance, allows the intrinsic base profile to be kept shallow, so it is well suited to a SiGe-base HBT. A 2-μm-wide BPSG/SiO 2 refilled trench was introduced to reduce substrate capacitance by reducing its sidewall element. This makes it possible to obtain a 95-GHz cut-off frequency and ultra-high-speed emitter-coupled-logic (ECL) circuit with an 8.0-ps gate-delay. As applications for these SiGe HBTs, various ICs for optical-fiber-link systems have been developed. These include a 1/8 static frequency divider with a maximum operating frequency of up to 50 GHz, a time-division multiplexer and a demultiplexer operating at 40 Gb/s, a preamplifier with a bandwidth of 35 GHz, an AGC amplifier core with a bandwidth of 32 GHz, and a decision circuit operating at 40 Gb/s.

GaAs FET characterization in a quasi-monolithic Si environment

Abstract: GaAs FET chips are planar embedded in a high resistivity silicon substrate and characterized up to 40 GHz in a coplanar environment. Hybrid interconnects (bonding wires) are replaced by thin film ones (air bridges). Small signal equivalent circuit extraction results confirm the expected low parasitic inductance values. These are reduced by more than 50% of the typical bonding wire interconnects.

Stray capacitance modeling of inductors by using the finite element method

Abstract: Stray capacitance modeling of an inductor is essential for its accurate equivalent circuit modeling. The stray capacitance determines the inductor's performance and upper frequency limit. In this paper, a method is proposed for modeling the distributed stray capacitance of inductors by the finite element method and a node-to-node lumped capacitance network. The effects of the wire insulation layer, ferrite core, the number of segments used to model the circumference of the wire cross section, the pitch and coil-to-core distances, and the capacitance between non-adjacent turns, etc., on the inductors' self-capacitance and calculation accuracy, have all been considered. The calculated equivalent lumped stray capacitance for a rod inductor with ferrite core is compared to that estimated from measurement. Good agreement between them has been observed.

Electronic device for smoothing a charge current peak in RLC output stages of switching step-up regulators

Abstract: An electronic device smoothes a charge current peak in RLC output stages of switching step-up regulators, which stages include an input terminal and an output terminal with an inductance and a parasitic resistance in series therebetween, the latter corresponding to the series parasitic resistance of the inductance, and a capacitor connected between the output terminal and a ground. The device comprises a parallel of a resistor and a controlled switch connected between the inductance and the output terminal of the stage upstream of the capacitor. Advantageously, the switch would only be open during the charge transient of the capacitor.

Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-/spl mu/m pMOSFET's

Abstract: Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFET's. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p/sup +/ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p/sup +/ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF/sub 2/ and the amorphization rate of substrate. Therefore, in sub-0.25-/spl mu/m era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p/sup +/ extension of 0.15 /spl mu/m pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%.

Analysis on voltage unbalance between the inner and outer devices in three level IGBT converters

Abstract: In this article, the voltage unbalance between the inner and outer IGBT of the NPC (neutral-point-clamping) three level converter is studied in detail. The keys of this task are to use a method-"step-by-step method" and to understand the basic conception that the parasitic inductance is relevant to the dimension of the loop and the value in proportion. It can be seen that the very reasons for the unbalance are the unique structure of NPC three level circuit and the parasitic inductance in the snubber circuit. Finally the designing tips for testing the snubber circuit are given. The simulation and experimental results demonstrate the validity of the analysis.

NbN circuits and packaging for 10 Kelvin IR focal plane array sensor signal processing

Abstract: Infrared (IR) focal plane array (FPA) imaging signal processing circuits, built in NbN and operating at 10 Kelvin, are presented. An ADC chip and digital signal processing chip are mounted on a 1.25 inch multi-chip module (MCM) with high bandwidth, low impedance interconnect. The populated MCM is designed to be installed into a module housing for operation with the cryogenic IR FPA. The 12-bit NbN SFQ counting ADC, previously used in a single chip version of the IR focal plane array sensor test system, is now implemented in an improved NbN process which includes a ground plane. Considerable attention has been focused on reducing parasitic inductance to compensate for the high characteristic inductance of the NbN films. These design improvements increase operating margins and circuit yield and make the ADC more robust in the presence of external system noise. Data from a bit-serial subtraction circuit to be used for pixel-by-pixel background subtraction is also presented. Finally, the design and electrical qualification of the physical package is described.

Simulation of Substrate Coupling with Special Regard to Shielding in High-Speed Si/SiGe Bipolar ICs

Abstract: Due to the increasing operating speed, the parasitic influence of the substrate in advanced Si and SiGe bipolar ICs tends to become more and more important and must be accurately taken into account already during circuit design. Moreover, the parasitic substrate coupling calls for shielding measures whose effectiveness at very high frequencies must be carefully checked as well. Therefore, in this paper a procedure for substrate modeling is described that has already been applied successfully in practice. For this, the numerical simulator SUSI has been developed and used to calculate the behavior of the substrate from the layout and from technological data. It has been verified by on-wafer measurements up to 40 GHz, as will be shown here for long-and short-distance substrate coupling with and without shielding. As an important application of SUSI, the reduction of substrate coupling by guard rings or by a, channel stopper layer is demonstrated. It is shown that shielding measures, however, can lose their effectiveness at very high frequencies due to the parasitic inductance of their metalization. Moreover, the results of the numerical simulation can be used to derive equivalent circuits which are necessary to model the influence of the substrate in circuit simulation.

Low cost broadband microstrip antenna for satellite-TV reception

Abstract: A broadband microstrip antenna for DBS (direct broadcasting by satellite) reception is presented. DBS in Europe requires a linear polarisation, a relative bandwidth of 17.5% (from 10.70 GHz to 12.75 GHz) and a cross-polarisation less than -20 dB. According to these requirements, a dual polarised aperture coupled microstrip antenna was designed in two steps. In the first step, a new disposition of the feeding lines was used. A single patch element permits to obtain a bandwidth of more than 26% whereas an additional patch element as a parasitic element is currently used in the literature to increase the bandwidth. In the second step, a perforated patch element was used in order to ameliorate the cross-polarisation.

Smart power component

Abstract: A power component is proposed which reliably switches inductive loads and has a current detection element to detect the current through the inductive load. The component includes a protective element which is connected to the source terminals of the sense element and of the actuator. The protective element protects against parasitic effects between the sense element and the actuator.

Photoelectric conversion element and photoelectric converter

Abstract: PROBLEM TO BE SOLVED: To increase the fabrication yield by forming the section from the drain region of a junction type field effect transistor to a semiconductor substrate using the same conductivity type semiconductor and constituting a photoelectric converter by arranging photoelectric conversion elements in matrix SOLUTION: The N type drain region 16 of a junction type field effect transistor (JFET) 2 is connected electrically with a heavily doped N type semiconductor substrate 100 to obtain a photoelectric conversion element A photoelectric converter is then constituted by arranging a large number of photoelectric conversion elements in matrix and a drain voltage is supplied to each JFET 2 from a drain electrode formed around the matrix through the heavily doped N type semiconductor substrate 100 Since the thickness of the semiconductor substrate 100 is thicker by a factor of two fingers than the junction depth of a heavily doped diffusion layer 16 forming the drain region, parasitic resistance is reduced significantly to cause no problem of voltage drop Consequently, drain interconnection can be eliminated

Semiconductor device having high-density capacitor elements and manufacturing method thereof

Abstract: A semiconductor device including a capacitor element which has a high withstand voltage, a large capacitance, and little parasitic resistance and parasitic capacitance. On interlayer insulating films provided on a semiconductor device, there is formed a lower electrode of a capacitor element coated with an alumina thin film through use of a portion of a first metal layer to be used for forming a first wiring layer. An electrode to constitute a portion of an upper electrode of the capacitor element is formed from a second metal layer so as to come into contact with the alumina thin film provided on the surface of the lower electrode. On the electrode, an upper electrode of the capacitor element is formed through use of a portion of a third metal layer to be used for forming a second wiring layer. Further, an lead electrode connected to the lower electrode is formed through use of a portion of the third metal layer by removal of a portion of the alumina thin film provided on the surface of the lower electrode.

Influence of parasitic inductance on serial fixed type switched-capacitor transformer

Abstract: Influence of parasitic inductance on a serial fixed type switched-capacitor (SC) transformer is analyzed in comparison with that in the case of a series-parallel type SC transformer. As the result show, it is clear that the influence of the parasitic inductance on the serial fixed type is extremely large as compared with that of the series-parallel type. In addition, an equivalent circuit is derived which is very useful for easily obtaining the inrush current and the overshoot of the output voltage in the serial fixed type.

A new analytical model to determine the drain-source series resistance of FOLD MOSFET

Abstract: An analytical model to determine the intrinsic drain-source series resistance of a fully overlapped lightly doped drain (FOLD) MOSFET is presented. Considering outer and inner fringing capacitances and the depletion of the n- surface caused by the normal electric field from the gate, I-V characteristics, transconductance, drain conductance, channel resistance, cut-off frequency and transit time are studied. It is shown that, because of the lesser parasitic resistance of the FOLD structure, the device provides higher current driving ability than the lightly doped drain and can suppress hot carrier degradation by avoiding degradation due to the depletion of the n- region by electrons trapped in the sidewall. Some of the predictions of the model are verified with experimental data.