Showing papers on "Polycrystalline silicon published in 2001"

Semiconductor thin film forming method, production methods for semiconductor device and electrooptical device, devices used for these methods, and semiconductor device and electrooptical device

Abstract: An object of the present invention is to provide a method for easily forming a polycrystalline semiconductor thin-film, such as polycrystalline silicon having high crystallinity and high quality, or a single crystalline semiconductor thin-film at inexpensive cost, the crystalline semiconductor thin-film having a large area, and to provide an apparatus for processing the method described above. In forming a polycrystalline (or single crystalline) semiconductor thin-film ( 7 ), such as a polycrystalline silicon thin-film, having high crystallinity and a large grain size on a substrate ( 1 ), or in forming a semiconductor device having the polycrystalline (or single crystalline) semiconductor thin-film ( 7 ) on the substrate ( 1 ), a method comprises forming a low-crystallization semiconductor thin-film ( 7 A) on the substrate ( 1 ), and subsequently heating and cooling this low-crystallization semiconductor thin-film ( 7 A) to a fusion, a semi-fusion, or a non-fusion state by flash lamp annealing to facilitate the crystallization of the low-crystallization semiconductor thin-film, whereby a polycrystalline (single crystalline) semiconductor thin-film ( 7 ) is obtained. A method for forming the semiconductor device and an apparatus for processing the methods are also disclosed.

High-cycle fatigue and durability of polycrystalline silicon thin films in ambient air

Abstract: To evaluate the long-term durability properties of materials for microelectromechanical systems (MEMS), the stress-life ( S / N ) cyclic fatigue behavior of a 2-μm thick polycrystalline silicon film was evaluated in laboratory air using an electrostatically actuated notched cantilever beam resonator. A total of 28 specimens were tested for failure under high frequency (∼40 kHz) cyclic loads with lives ranging from about 10 s to 34 days (3×10 5 to 1.2×10 11 cycles) over fully reversed, sinusoidal stress amplitudes varying from ∼2.0 to 4.0 GPa. The thin-film polycrystalline silicon cantilever beams exhibited a time-delayed failure that was accompanied by a continuous increase in the compliance of the specimen. This apparent cyclic fatigue effect resulted in an endurance strength, at greater than 10 9 cycles, of ∼2 GPa, i.e. roughly one-half of the (single cycle) fracture strength. Based on experimental and numerical results, the fatigue process is attributed to a novel mechanism involving the environmentally-assisted cracking of the surface oxide film (termed reaction-layer fatigue). These results provide the most comprehensive, high-cycle, endurance data for designers of polysilicon micromechanical components available to date.

Temperature-dependent thermal conductivity of undoped polycrystalline silicon layers

Abstract: Polycrystalline silicon is used in microelectronic and microelectromechanical devices for which thermal design is important This work measures the in-plane thermal conductivities of free-standing undoped polycrystalline layers between 20 and 300 K The layers have a thickness of 1 +m, and the measurements are performed using steady-state Joule heating and electrical-resistance thermometry in patterned aluminum microbridges The layer thermal conductivities are found to depend strongly on the details of the deposition process through the grain size distribution, which is investigated using atomic force microscopy and transmission electron microscopy The room-temperature thermal conductivity of as-grown polycrystalline silicon is found to be 138 W } m &1 }K &1 and that of amorphous recrystallized polycrystalline silicon is 22 W } m &1 }K &1 , which is almost an order of magnitude less than that of single-crystal silicon The maximum thermal conductivities of both samples occur at higher temperatures than in pure single-crystalline silicon layers of the same thickness The data are interpreted using the approximate solution to the Boltzmann transport equation in the relaxation time approximation together with Matthiessen’s rule These measurements contribute to the understanding of the relative importance of phonon scattering on grain and layer boundaries in polysilicon films and provide data relevant for the design of micromachined structures

Area sensor and display apparatus provided with an area sensor

Abstract: An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.

Results from 3-D silicon sensors with wall electrodes: near-cell-edge sensitivity measurements as a preview of active-edge sensors

Abstract: Silicon sensors with a three-dimensional (3-D) architecture, in which the n and p electrodes penetrate through the entire substrate, have been successfully fabricated. The electrode spacing can be less than the substrate thickness, allowing short collection paths, low depletion voltages, and large current signals from rapid charge collection. This paper gives results when the cylindrical electrodes of the earlier papers are replaced by a combination of cylindrical and wall electrodes-ones in which a trench, rather than a hole, is filled with doped polycrystalline silicon. The detection efficiency remains high to within a few micrometers of these wall electrodes, and is an indication that similar high efficiencies should be achievable near the physical edges of the proposed active-edge sensors.

Trench MOSFET with double-diffused body profile

Abstract: A trench MOSFET device and process for making the same are described. The trench MOSFET comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a plurality of trenches within the epitaxial layer; (d) a first insulating layer, such as an oxide layer, lining the trenches; (e) a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer; (f) one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions; each trench body region and each termination body region comprising (1) a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and (2) a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region; and the second region being disposed above the first region; and (g) a plurality of source regions of the first conductivity type positioned adjacent the trenches within upper portions the trench body regions.

An investigation of laser annealed and metal-induced crystallized polycrystalline silicon thin-film transistors

Abstract: We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC) With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm/sup 2//Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V Similar trends occur for both p- and n-type material A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure The MILC material in particular exhibits a very high generation state density of /spl sim/10/sup 19/ cm/sup -3/ which is reduced by an order of magnitude in L-MILC material The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors

On-current modeling of large-grain polycrystalline silicon thin-film transistors

Abstract: Large-grain excimer laser-annealed polysilicon TFTs are studied. Due to the large grain size of the polysilicon film (about 2.5 /spl mu/m), we propose a model for the on-current (above threshold voltage) taking into account the number of grain boundaries within the channel. This linear-region model considers grain and grain boundaries as two noncorrelated regions within the channel of a polysilicon TFT. The trap density at the grain boundaries and the device parameters involved in this model are determined by fitting the experimental transfer characteristic in the linear regime. Moreover, we show that the proposed model provides reliable results within a temperature range from 150 K to 300 K. Finally, it serves to optimize the energy density of laser annealing and to make predictions about polysilicon TFT technology, since TFTs performances versus grain size plots can be obtained.

Semiconductor device, semiconductor memory device and manufacturing method, and portable information equipment

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, having a channel region made of a polycrystalline semiconductor having a small off-leakage and a small unevenness of the off-leakage at each element. SOLUTION: A TFT is formed on an insulating board 1. The channel region of the TFT is made of a polycrystalline silicon. A thickness of this channel region is 5 nm or less, and the width of the channel region is 0.3 μm or less. As a result, off-leakage of the TFT can be suppressed to be very small, and the unevenness of the TFT can be suppressed.

Method of optimizing channel characteristics using multiple masks to form laterally crystallized ELA poly-Si films

Abstract: A method is provided to optimize the channel characteristics of thin film transistors (TFTs) on polysilicon films. The method is well suited to the production of TFTs for use as drivers on liquid crystal display devices. The method is also well suited to the production of other devices using polysilicon films. Regions of polycrystalline silicon can be formed with different predominant crystal orientations. These crystal orientations can be selected to match the desired TFT channel orientations for different areas of the device. The crystal orientations are selected by selecting different mask patterns for each of the desired crystal orientation. The mask patterns are used in connection with lateral crystallization ELA processes to crystallize deposited amorphous silicon films.

Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors

Abstract: In this letter, we present experimental data showing that hot-carrier stress in laser annealed polycrystalline silicon thin-film transistors provokes an anomalous turn-on voltage variation. Although under various hot-carrier stress intensities the maximum transconductance degradation shows the same power-time dependent law, turn-on voltage can exhibit different behaviors. This observation lead to the conclusion that turn-on voltage depends on two different degradation mechanisms: injection of hot carriers into the gate oxide and degradation of grain boundaries. We show that these two mechanisms may be distinguished since they obey different power-time dependent laws as a function of stress duration.

Selective Deposition of Thin Copper Films onto Silicon with Improved Adhesion

Abstract: Metallization plays a key role in the production process of integrated devices. Recently, copper (Cu) has been proposed as an alternative material to aluminum to address the need for metallic thin films with low resistivity and high electromigration resistance. 1 As a consequence, great attention has been paid to electrochemical processes, which enable the deposition of metallic copper at low temperatures with low costs. Copper electroless deposition has been shown to selectively plate silicon (Si) substrates and structures with high aspect ratios and large structural heights. 2,3 However, this method requires a pretreatment to activate the surface. Selectivity is achieved only to the extent that the activating treatment can be made selectively. In addition, many studies have also been carried out on the galvanic deposition of copper from fluoride containing solutions.4-11 In contrast to electroless deposition, galvanic displacement deposition requires no prior activation of the surface and is truly selective to silicon surfaces. Thus, it provides an attractive deposition method for copper interconnects or seed layers for subsequent metallization.4 Galvanic displacement is also a promising avenue for the integration of metals in micromechanical devices, due to its conformal nature and high substrate selectivity. Despite these attractive features, a crucial issue in the aforementioned processes is the lack of adhesion of copper to the Si substrate, which may severely constrain their application. 12 In particular, copper films deposited by galvanic displacement fail the qualitative Scotch tape test. In this paper, we report a process for the galvanic deposition of copper onto silicon from fluoride-containing solutions. Thin copper films with reflective and smooth surfaces and excellent adhesion to silicon are obtained. Results on plating of microelectromechanical systems (MEMS) after release are also presented. Polycrystalline silicon and single crystalline Si(100) and Si(111), p- or n-type, and analytical grade chemicals were used. Samples were ultrasonicated in acetone and, after drying with nitrogen flux, etched in concentrated hydrofluoric acid for 10 min. The hydrogenterminated surfaces thus obtained were rinsed, dried, and immersed in the plating solution. The following additives were used to prepare the aqueous solution: ammonium fluoride (NH 4 F 40%) 50 vol %, copper sulfate (CuSO 4 ·5H 2 O) 0.01 M, ascorbic acid (C 6 H 8 O 6 ) 0.01 M, sodium potassium tartrate (KNaC 4 H 4 O 6 ·4H 2 O) 0.005 M, and methanol 30 vol % (percentages are referred to the final solution volume).13 The pH of the solution was 7.5. Room temperature (25°C) and gentle agitation of samples were used. Samples were finally rinsed in deionized water and dried with nitrogen flux. The adhesion of the copper film to the substrate is strongly related to the presence of ascorbic acid in solution. The absence of the acid results in the formation of a copper film which fails the standard scotch tape test. Because we have observed a similar effect when ascorbic acid was substituted with fumaric acid, and both acids are

Atomic scale measurements of the interfacial electronic structure and chemistry of zirconium silicate gate dielectrics

Abstract: We have examined the interfaces in Zr-silicate gate dielectrics grown on Si substrates using electron energy loss spectroscopy. The Zr-silicate interface is found to be stable with the Si substrate and the polycrystalline silicon (poly-Si) electrode under annealing to 1050 °C. At this interface, a 0.35 nm wide Zr-free interface region is observed in the as-deposited film, and does not change on annealing. The Zr-free region is too thin to take on the bulk SiO2 electronic structure, and thus is unlikely to compromise the dielectric properties of the device. For films with an Al electrode, a 2 nm reaction layer forms at the Zr-silicate interface.

Thin film transistor having high mobility and high on-current and method for manufacturing the same

Abstract: In a thin film transistor (TFT) including an insulating substrate and a polycrystalline silicon island formed on the insulating layer, a grain size of the polycrystalline silicon island is elongated along one direction. A source region, a channel region and a drain region are arranged in the polycrystalline silicon island in parallel with the direction.

Method of crystallizing a silicon thin film and semiconductor device fabricated thereby

Abstract: The present invention relates to a method of crystallizing an amorphous silicon thin film by thermal annealing the amorphous silicon thin film vapor deposited on a substrate in order to form a polycrystalline silicon thin film, and a semiconductor device fabricated by the method. According to the present invention, it is constructed such that a light-absorbing layer having absorbance of light much higher than that of the substrate or the amorphous silicon thin film is formed around the amorphous silicon thin film and is heated by a lamp when crystallizing the amorphous silicon thin film vapor deposited on the substrate by rapid annealing. Therefore, the temperature of the amorphous silicon thin film can be raised while restraining the increase in temperature of the substrate to the utmost. Accordingly, the amorphous silicon thin film can be crystallized without deformation of the substrate.

Method of forming semiconductor film, method of manufacturing semiconductor device and electro-optical device, and apparatus used for executing the methods, and the semiconductor device and electron-optical device

Abstract: PROBLEM TO BE SOLVED: To provide a method which can form a polycrystalline or monocrystalline semiconductor thin film, such as polycrystalline silicon of high crystallization percentage and high quality, etc., easily and at low cost and with large area, and a device to put this method into practice. SOLUTION: A formation method for a polycrystalline (or monocrystalline) semiconductor thin film or a manufacturing method for a semiconductor device, and a device to put it into practice, includes a step where a polycrystalline (or monocrystalline) semiconductor film 7 is obtained, by accelerating the crystallization of a low-class crystalline semiconductor film 7A by the heating or cooling in fusion or half fusion, or non-fusion state by applying flash lamp annealing to this low-class crystalline semiconductor film 7A after forming the low-class semiconductor film 7A on a substrate 1, when forming the polycrystalline (or monocrystal) semiconductor film 7, such as a polycrystalline silicon film of high crystallization percentage and large grain diameter, etc., on the substrate 1 or when manufacturing the semiconductor device, having a polycrystalline (or monocrystal) semiconductor film 7 on the substrate 1.

Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location

Abstract: Dependence of transistor characteristics on the grain-boundary location in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) has been analyzed using device simulation. In the linear region, degradation is similar wherever the grain boundary is located. On the other hand, in the saturation region, degradation is less when the grain boundary is in the pinch-off region near the drain edge and degradation is similar when the grain boundary is elsewhere. Although this dependence is similar to the dependence on the trap location in single-crystal silicon transistors, the mechanism is different. This dependence in poly-Si TFTs is because the coulombic potential barrier caused by the grain boundary is lowered in the high electric field in the pinch-off region. This is a kind of Poole–Frenkel effect.

Protective layer for quartz crucibles used for silicon crystallization

Abstract: A thermodynamically stable, protective coating layer is applied by thermal spray technique to the inner and outer surfaces of a quartz crucible used for mono or polycrystalline silicon crystallization processing, inhibiting fusion between the silicon melt and the vitreous silica of the crucible, contamination of the silicon melt by contaminants released from the crucible by devitrification, and any chemical reaction occurring between the crucible and any supporting graphite structure A powdered form of a suitable protective coating material compatible with high temperature plasma spray techniques, such as magnesium zirconate, barium zirconate, or stabilized zirconium oxide, is fed into a high temperature and high speed plasma jet directed at the crucible The powder particles are softened or melted in the jet and deposited on the surfaces of the quartz crucible, and allowed to cool and harden into a protective coating

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Abstract: Microcrystalline silicon (μc-Si:H) thin films were prepared at 300 °C on glass. Their structure and transport properties were studied in a wide range of film thickness ranging from 10 nm to 1 μm. The crystal fraction increases monotonously from ∼64% to ∼100% as film thickness increases. Electron mobility first increases with increasing film thickness at thicknesses smaller than 50 nm but saturates at larger thickness. This mobility behavior is explained by percolation transport through crystalline grains. These results are different from those obtained with preferentially oriented polycrystalline silicon films. It is related to the difference in the microstructure evolution in which subsequent film growth is influenced by the growth surface structure. A single-electron transistor fabricated in 30-nm-thick μc-Si:H exhibits Coulomb blockade effects at 4.2 K. This result indicates that amorphous phases which exist between crystalline grains behave as tunnel barrier for electrons.

Tribology on the macroscale to nanoscale of microelectromechanical system materials: A review

Abstract: Silicon-based microelectromechanical system (MEMS) devices are made from single-crystal silicon, polycrystalline silicon (polysilicon) films obtained by low-pressure chemical vapour deposition and certain ceramic films. For high-temperature applications, SiC films are being developed to replace polysilicon films. Tribology in the MEMS devices requiring relative motion is of importance. Atomic force microscopy/friction force microscopy (AFM/FFM) and nanoindentation techniques have been used for tribological studies on a microscale to nanoscale on materials of interest. These techniques have been used to study surface roughness, friction, scratching and wear, indentation and boundary lubrication of bulk and treated silicon, polysilicon films and SiC films, Macroscale friction and wear tests have also been conducted using the ball-on-flat tribometer. Measurements of microscale and macroscale frictional forces show that friction values on both scales of all the silicon samples are about the same for d...

Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors

Abstract: A technique to extract trap states at the oxide-silicon interface and grain boundary has been developed for polycrystalline silicon thin-film transistors with large grains. From the capacitance–voltage characteristic, the oxide-silicon interface traps can be extracted. Potential and carrier density are also extracted. From the potential, carrier density, and current–voltage characteristic, the grain boundary traps can be extracted by considering the potential barrier at the grain boundary. Since these trap states are sequentially extracted, any shape of energy distribution of the trap states can be extracted. The correctness of this extraction technique is confirmed by comparison with two-dimensional device simulation.

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Abstract: Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP/sup TMI/) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

Crystalline Silicon Photovoltaic Cells

Abstract: The photovoltaic industry is in a phase of rapid expansion, growing at over 30 % per annum over recent years. Although technologies based on thin-film compound and alloy solar cells are under active development, most commercial solar cells presently use self-supporting bulk crystalline or multicrystalline silicon wafers, similar to those used in microelectronics. The laboratory performance of these cells, at 25 % solar energy conversion efficiency, is now approaching thermodynamic limits, with the challenge being to incorporate these improvements into low-cost commercial products. Improvements in cell optical design, particularly in their ability to “trap” weakly absorbed light, has also led to a growing interest in thin-film cells based on polycrystalline silicon, having advantages over other thin film photovoltaic candidates.

Method for darkening pixel

Abstract: Peripheries of a contact 26 for connecting a polycrystalline silicon layer 20 to a pixel electrode 28 are cut by a laser to form a cut area 50. By this cut area 50, the polycrystalline silicon layer 20 around the contact 26 is also cut. In consequence, a TFT 24 is separated from the pixel electrode 28 and a supplemental capacitor electrode 32 to reliably accomplish darkening.