Showing papers on "Programmable logic array published in 1996"

Programmable active memories: reconfigurable systems come of age

Abstract: Programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM's offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM's, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions; no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM's. By Noyce's law, we predict by how much the performance gap will widen with time.

Time multiplexed programmable logic device

Abstract: A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiments, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.

Second-layer phase change memory array on top of a logic device

Abstract: The present invention is a computational unit comprising a logic processing device (10), and a memory array (30) deposited on top of and communicating with the logic processing device. More specifically, the present invention is a computational unit comprising a logic processing device (10), and electrically erasable phase change memory (30) deposited on top of and communicating with the logic processing device.

Integrated circuit with field programmable and application specific logic areas

Abstract: A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

System and method for dynamically reconfiguring a programmable gate array

Abstract: In each of multiple logic cells of a Programmable Gate Array ("PGA"), a programming array is provided having multiple programming words therein. Each of the programming words is engagable to control the configuration of the logic cell. The programming words are selectively engaged such that multiple functions are performed by the logic cell within the PGA. As a result, a PGA with a number of virtual logic cells in excess of actual physical logic cells is provided. The PGA therefore has the capability to emulate a PGA with a larger number of logic cells than it physically has.

Chemical Wave Logic Gates

Abstract: Logic gates based on chemical wave propagation in geometrically constrained excitable media are demonstrated in a Belousov−Zhabotinsky membrane system. The catalyst of the reaction is printed in specific predetermined patterns with geometries designed to provide various logic operations. Computational studies of the serial coupling of elements to form multicomponent gates and general chemical wave circuitry are presented.

Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density

Abstract: Field-Programmable Gate Arrays are interesting, general-purpose computational devices because (1) they have high computational density and (2) they have finegrained control of their computationalresources since each gate is independently controlled. The earlier provides them with a potential 10 advantage in raw peak performance density versus modern microprocessors. The later can afford a 32 advantage on random bit-level computations. Nonetheless, typical FPGA usage seldom extracts this full density advantage. DPGAs are less computationally dense than FPGAs, but allow most applications to achieve greater, yielded computational density. The key to unraveling this potential paradox lies in distinguishing instruction density from active computing density. Since the storage space for a single instruction is inherently smaller than the computational element it controls, packing several instructionsper computationalunit increases theaggregate instruction capacity of the device without a significant reduction in computational density. The number of different instructions executed per computational task often limits the effective computational density. As a result, DPGAs can meet the throughput requirements of many computing tasks with 3-4 less area than conventional FPGAs. 1 Computational Area “How big is a computation?” The design goal for “general-purpose” computing devices is to develop a device which can: implement desired computational tasks perform the computation at the desired latency or throughput realize the implementation at minimal cost – usually silicon area As device designers we are concerned with the area which a computational element occupies and its latency or throughput. We know, for example, that a four input Lookup Table (4-LUT) occupies roughly 640K 2 (e.g. 0.16mm2 in a 1 CMOS processor ( 0 5 )) [1] [9]. Thus, we get a 4-LUT density of 1.6 4-LUTs per one million 2 of area. At the same time, we notice that the descriptive density of 4-LUT designs can be much greater than the 4-LUT density just observed. That is, the LUT configuration is small compared to the network area so that an idle LUT can occupy much less space than an active one. For illustrative purposes, let us assume that it takes 200 bits to describe the configuration for one 4-LUT, which is typical of commercial FPGA devices. A 64Mb DRAM would hold 335K such configurations. Since a typical 64Mb DRAM is 6G 2, we can pack 56 4-LUT descriptions per one million 2 of area – or about 35 the density which we can pack 4-LUTs. In fact, there is good reason to believe that we can use much less than 200 bits to describe each 4-LUT computation [3], making even greater densities achievable in practice. Returning to our original question, we see that there are two components which combine to define the requisite area for our general-purpose device: 1. Nd – the total number of 4-LUTs in the design – the descriptive complexity 2. Na – the total number of 4-LUTs which must be evaluated simultaneously in order to achieve the desired task time or computational throughput – the parallelism required to achieve the temporal requirements In an ideal packing, a computation requiringNa active FPD’96 -Fourth Canadian Workshop of Field-Programmable Devices May 13-14, 1996, Toronto, Canada Figure 1: DPGA LUT and Interconnect Primitives compute elements and Nd total 4-LUTs, can be implemented in area: Acompute Na ALUT Nd ALUT config mem 1 In practice, a perfect packing is difficult to achieve due to connectivity and dependency requirements such thatN d Nd configuration memories are required.

Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)

Abstract: We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.

Apparatus having a plurality of programmable logic processing units for self-repair

Abstract: An information processing apparatus with programmable function and self-repair function which can deal with multiple troubles the information processing apparatus includes a logic processing unit formed of logic forming elements for realizing a predetermined function; spare logic processing units that can be reconfigured of logic forming elements to reproduce the predetermined function of the logic processing unit; a data holding unit for holding forming data in the logic processing unit; a fault detecting unit for detecting a fault occurrence in the logic processing unit; and a reconfiguring unit for reconfiguring the spare logic processing unit having a logic circuit configuration similar to the logic processing unit, based on configuration data read out of the data holding unit, when the fault detecting unit detects a fault occurrence The information processing apparatus can automatically reconfigure the system to reproduce its original normal function of a faulty forming element

VHDL for Programmable Logic

Abstract: (NOTE: Each chapter begins with a Summary and ends with a Summary, Breakout Exercises and Problems). 1. Introduction. Why Use VHDL? Shortcomings. Using VHDL for Design Synthesis. Design Tool Flow. Our System. Font Conventions. 2. Programmable Logic Primer. Introduction. Why Use Programmable Logic? What Is a Programmable Logic Device? Simple PLDs. What Is a CPLD? What Is an FPGA? PREP Benchmarks. Future Direction of Programmable Logic. 3. Entities and Architectures. A Simple Design. Design Entities. Identifiers, Data Objects, Data Types, and Attributes. Common Errors. 4. Creating Combinational and Synchronous Logic. Design Example. Combinational Logic. Synchronous Logic. Designing a FIFO. Common Errors. Test Benches. 5. State Machine Designs. A Simple Design Example. A Memory Controller. Mealy State Machines. Additional Design Considerations. 6. Hierarchy in Large Designs. Case Study: The AM2901. Case Study: A 100BASE--T4 Network Repeater. 7. Functions and Procedures. Functions. Procedures. About Subprograms. 8. Synthesis and Design Implementation. Design Implementation: An Example. Synthesis and Fitting. CPLDs: A Case Study. FPGAs: A Case Study. 9. Optimizing Datapaths. Pipelining. Resource Sharing. Magnitude Comparators. Fast Counters. 10. Creating Test Benches. Approaches to Writing Test Benches. Overloaded Read and Write Procedures. Afterword. Review. Where To Go from Here. Appendix A: Viewing On-line Documentation and Installing Warp. Appendix B: Reserved Words. Appendix C: STD_logic_1164 Package. Appendix D: Quick Reference Guide. Glossary. Bibliography. Index.

Integrated drivers for flat panel displays employing chalcogenide logic elements

Abstract: The present invention defines a family of logic circuitry comprising at least one logic gate. Each logic gate comprises a plurality of chalcogenide threshold switches (OTS1, OTS2, OTS3). The logic gates of the present invention use a chalcogenide threshold switch (OTS3) as a means of discharging load capacitance and resetting logic gate output. The present invention also defines a display driver for driving a flat panel display having row and column driving lines. The display driver comprises logic gates where each logic gate is comprised of chalcogenide threshold switches (OTS1, OTS2, OTS3).

A capacitive threshold-logic gate

Abstract: A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

High speed programmable logic architecture

Abstract: Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. The PLD uses BiCMOS circuit elements to make use of the speed advantages of bipolar technology while also enjoying the limited power consumption of CMOS technology.

An approach for testing programmable/configurable field programmable gate arrays

Abstract: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a physical and behavioral characterization; this permits the detection of a single fault, as either a stuck-at or a functional fault. A general approach which regards testing as can application for the reconfigurable FPGA, is then proposed. It is shown that different arrangements of disjoint one-dimensional arrays with unilateral horizontal connections and common vertical input lines provide a very good solution. A further feature that is considered for array testing, is the relation between the configuration of the logic blocks and the number of I/O pins in the chip. As an example, the proposed approach is applied for testing the Xilinz 4000 family of FPGAs.

Hybrid FPGA Architecture

Abstract: This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The proposed Hybrid FPGA is evaluated by manually technology mapping a set of circuits into the new architecture and estimating the total chip area needed for each circuit, compared to the area that would be required if only LUTs were available. Preliminary results indicate that compared to LUT-based FPGAs the Hybrid offers savings of more than a factor of two in terms of chip area.

Tristate structures for programmable logic devices

Abstract: A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

Diagnosing Programmable Interconnect Systems for FPGAs

Abstract: This paper deals with the diagnosis of field programmable interconnect systems (FPIS) in which nets are connected through programmable switches arranged in grids. A hierarchical approach to diagnosis is proposed. The conditions by which such process yields full diagnosis and the characteristics of the programming sequence, are fully proved. For a FPIS consisting of a k x k grid array, the number of tests is given by 4 + 4kn^2, while the number of programming steps is 4nk + 1, where n is the dimension of a grid. The application of this technique to commercially available FPIS in FPGAs, is discussed.

Embedded memory for field programmable gate array

Abstract: A programmable logic device has a configuration memory which is partitioned so that it includes at least one subarray available through the programmable interconnect of the user configurable logic to be used as user memory. Subarrays of the configuration memory have independent access logic coupled with them, and coupled to the user logic array so that they may be used independently as user memories. Subarray memory access logic is provided for each subarray of memory elements, and connected to the logic cell array, and optionally to the plurality of input/output cells on the device, including a subarray decoder used for selecting addressed memory elements in the corresponding subarray in response to address signals and control signals supplied across the interconnect structures of the logic cell array, and a subarray I/O path used to provide input and output data signals between the interconnect structures of the logic cell array and addressed memory elements in the subarray. Thus, each subarray of memory elements, its corresponding subarray decoder and subarray I/O path, are independently configurable in the programmable logic device for use as user memory.

Microprocessor with distributed registers accessible by programmable logic device

Abstract: A chip (500) includes a programmable logic device and a microprocessor (506), wherein at least one of the associated registers (501A, 501B) of the microprocessor (506) is distributed in the programmable logic device. The distributed register (501A, 501B) is coupled to both the microprocessor (506) and the programmable logic device. In this manner, the microprocessor (506) has the ability to access the register and place a value into the programmable logic device all in one clock cycle. Additionally, the logic functions in the programmable logic device are also advantageously available to the microprocessor (506).

Logic cell and routing architecture in a field programmable gate array

Abstract: The present invention provides for an FPGA integrated circuit having an array of logic cells (10) and interconnect lines (X1, X2, X3) interconnected by programmable switches (24-29), each formed from a nonvolatile memory cell. The logic cell (10) is designed to provide logic or memory functions according to the setting of programmable switches (30-33) within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between wiring segments.

DRAM memory cell for programmable logic devices

Abstract: A plurality of DRAM cells are used to store the state of the programmable points in a programmable logical device (e.g., a field programmable gate array or FPGA). An individual DRAM cell is used in conjunction with each programmable interconnect point (PIP) within the FPGA to hold a logical state indicating the connectivity state of the PIP. During a refresh cycle, each DRAM memory cell is loaded with its current logical state in order to maintain this state within the PIP. An information store contains duplicate data for each DRAM cell and this duplicate data is supplied and read during the refresh cycle in order to provide each DRAM cell with its proper logical state. In this manner, the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell. The information store can be a plurality of DRAM cells or the information store can be of non-volatile memory, for instance, read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), or of non-volatile magnetic storage.

Programmable array I/O - routing resource

Abstract: A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks

Abstract: We present a new approach for FPGA testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without area or performance penalties to the system function implemented by the FPGA, since the FPGA is reconfigured for normal system operation. An analysis of Look-Up Table (LUT) based FGPA architectures yields a general expression for the number of test sessions and establishes the bounds on FPGA logic resources required to minimize the number of BIST configurations required to completely test all of the programmable logic blocks of an FPGA.

Programmable logic controller computer system with micro field processor and programmable bus interface unit

Abstract: A programmable logic controller computer system is provided which achieves great flexibility in communication among the components of the system. The computer system includes a host programmable logic controller coupled by a field bus to a programmable bus interface unit. The programmable bus interface unit is located at a field station which includes a main bus to which a micro field processor and a plurality of I/O modules are coupled. The micro field processor is capable of locally processing I/O data from the I/O modules without involving the host PLC. A hand-held programmer is coupled to the programmable bus interface unit to permit the user to program an I/O map into the bus interface unit. The I/O map specifies mapping among the I/O modules, the micro field processor and the host programmable logic controllers. In this manner, communication among the I/O modules, the micro field processor and the host programmable logic controller is flexibly specified and controlled. Moreover, field bus traffic from the I/O modules back to the host programmable logic controller is significantly reduced.

Dynamic configurable elements for programmable logic devices

Abstract: A programmable logic device using dynamic programmable elements to store configuration data is refreshed by periodic writing of configuration data from the source memory into the dynamic programmable elements. The invention takes advantage of smaller sized dynamic programmable elements and eliminates the need to perform tedious read/sense operation for each refresh cycle.

Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA

Abstract: A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.

Method and system for enhanced drive in programmmable gate arrays

Abstract: In a programmable gate array ("PGA"), logic cells therein are programmed to create a combined output with enhanced current driving ability Specifically, a first logic cell is programmed to have a first output and a second logic cell is programmed to have a second output The first and second outputs are connected within the PGA forming a combined output having enhanced current driving ability by the first logic cell and the second logic cell The first and second logic cells are programmed with identical logic functions such that they operate in parallel

Asynchronous FPGA architectures

Abstract: Field programmable gate arrays (FPGAs) are of increasing importance as processor support devices, and as computational devices in their only right. Current synchronous FPGA architectures create problems for the implementation of asynchronous circuits, due to their creation of hazards, reordering of signals and lack of arbitration. The paper examines how the first generation of asynchronous FPGA architectures (MONTAGE, PGA-STC and STACC) tackle these problems.

On the viability of FPGA-based integrated coprocessors

Abstract: The paper examines the viability of using integrated programmable logic as a coprocessor to support a host CPU core. This adaptive coprocessor is compared to a VLIW machine in term of both die area occupied and performance. The parametric bounds necessary to justify the adoption of an FPGA-based coprocessor are established. An abstract field programmable gate array model is used to investigate the area and delay characteristics of arithmetic circuits implemented on FPGA architectures to determine the potential speedup of FPGA-based coprocessors. Analysis shows that integrated FPGA arrays are suitable as coprocessor platforms for realising algorithms that require only limited numbers of multiplication instructions. Inherent FPGA characteristics limit the data-path widths that can be supported efficiently for these applications. An FPGA-based adaptive coprocessor requires a large minimum die area before any advantage over a VLIW machine of a comparable size can be realised.

Directional bias and non-uniformity in FPGA global routing architectures

Abstract: This paper investigates the effect of the prefabricated routing track distribution on the area-efficiency of FPGAs. The first question we address is whether horizontal and vertical channels should contain the same number of tracks (capacity), or if there is a density advantage with a directional bias. Secondly, should the channels have a uniform capacity, or is there an advantage when capacities vary from channel to channel? The key result is that the most area-efficient global routing architecture is one with uniform (or very nearly uniform) channel capacities across the entire chip in both the horizontal and vertical directions. Several non-uniform and directionally-biased architectures, however, are fairly area-efficient provided that appropriate choices are made for the pin positions on the logic blocks and the logic array aspect ratio.