Showing papers on "Reference architecture published in 1991"

NUMA policies and their relation to memory architecture

Abstract: Multiprocessor memory reference traces provide a wealth of information on the behavior of parallel programs. We have used this information to explore the relationship between kernel-based NUMA management policies and multiprocessor memory architecture. Our trace analysis techniques employ an off-line, optimal cost policy as a baseline against which to compare on-line policies, and as a policyinsensitive tool for evaluating architectural design alternatives. We compare the performance of our optimal policy with that of three implementable policies (two of which appear in previous work), on a variety of applications, with varying relative speeds for page moves and local, global, and remote memory references. Our results indicate that a good NUMA policy must be chosen to match its machine, and confirm that such policies can be both simple and effective. They also indicate that programs for NUMA machines must be written with care to obtain the best performance.

Communication system concentrator configurable to different access methods

Abstract: A local net area network, or LAN, configuration is provided with a multiple generic LAN channel architecture which can be logically and dynamically changed. The configuration control can be applied to each module of the network and to each port of a module of a LAN hub. The architecture provides multiple LAN protocols to be used simultaneously, as needed, through protocol specific functions. Industry standard protocol such as: token bus, token ring, and fiber distributed data interface (FDDI), can be implemented using the generic channel architecture and its characteristics providing respective network functions. The architecture also provides a digital collision detection method and provides information necessary for precise network statistics monitoring. The token passing ring architecture provides a logical ring formation within the generic channel. A token passing bus architecture uses modified Ethernet™ architecture, and a hub management provides control for the generic multichannel and the LAN management provides protocol dependent network management. The architecture provided allows multiple hub management entities via hub mastership arbitration to provide a unique master for the hub management function.

Paradigm: a highly scalable shared-memory multicomputer architecture

Abstract: Paradigm (parallel distributed global memory), a shared-memory multicomputer architecture that is being developed to show that one can build a large-scale machine using high-performance microprocessors, is discussed. The Paradigm architecture allows a parallel application program to execute any of its tasks on any processor in the machine, with all the tasks in a single address space. The focus is on novel design techniques that support scalability. The key performance issues are identified, and some results to date from this work and experience with the VMP architecture design on which it is based are summarized. >

A local area network architecture for communication in distributed real-time systems

Abstract: Distributed real-time systems of the future will require specialized network architectures that incorporate new classes of services and protocols in order to support time-constrained communication. In this paper, we propose a new local area network architecture for such systems. This four-layered architecture is characterized by new classes of connection-oriented and connectionless services that take into account the timing constraints of messages. We describe various aspects of the logical link control layer of the architecture and various real-time protocols that may be employed at the medium access control layer in order to support the new classes of services. We also describe a homogeneous approach to the implementation of medium access control protocols to support both connection-oriented and connectionless services, based on a uniform window splitting paradigm.

PROXHY: a process-oriented extensible hypertext architecture

Abstract: This research describes a new architecture for hypertext environments. The architecture merges the process, object-oriented, and hypertext models to provide hypertext services to object-based, distributed, application components. Through this architecture, applications are integrated to form a comprehensive hypertext computing environment, allowing links to connect applications or objects in different applications. The architecture separates hypertext and application functionality so that multiple applications can use the facilities of a common hypertext layer. The design of the architecture is such that components can be extended or tailored in order to support future applications, multimedia objects, or the needs of specific applications or users. The process-based, object-oriented framework allows objects of arbitrary complexity to live and interact in a hypertext world. Additionally, the protocol and facilities which support component interaction provide location transparency, arbitrary object granularity, and parallel computation over a network. This dissertation provides a conceptual model of hypertext and a general architecture for hypertext system construction. Related literature from object-oriented programming, operating systems, multimedia applications, and database is discussed in terms of the architecture. A hypertext data model, computational model, and hypertext system taxonomy are used to discuss the capabilities of current hypertext systems. Interaction scenarios are provided in order to illustrate object interaction and the distribution of work among the components of the architecture. A prototype system, implemented to demonstrate the feasibility of the architecture, is discussed. The prototype illustrates all aspects of the architecture including distributed application and hypertext components, cross-application linking, and anchors acting as proxy objects for applications. Application scenarios, problems and limitations, and future research issues provide an understanding of the power of the architecture and its potential for impacting the design of next-generation hypertext systems.

Swift: a storage architecture for large objects

Abstract: The authors describe an input/output architecture called Swift that addresses the problem of storing and retrieving very large data objects from slow secondary storage at very high data rates. Swift addresses the problem of providing data rates required by digital video by exploiting the available interconnection capacity and by using several slower storage devices in parallel. Two studies have been performed to validate the Swift architecture: a simulation study and an Ethernet-based, proof-of-concept implementation. Both studies indicate that the aggregation principle proposed in Swift can yield very high data-rates. >

Computer Architecture and Logic Design

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A two-dimensional, distributed logic architecture

Abstract: The authors present a novel, very fine grain associative architecture. This architecture maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. Unlike other associative memory processors, this architecture uses a two-dimensional interconnect and a physically compact memory structure. Arithmetic operations are based on the use of a redundant number system. These features provide a high level of performance. This is particularly true for certain two-dimensional problems which can be solved very efficiently on the proposed architecture. >

The entropy reduction engine: integrating planning, scheduling, and control

Abstract: This paper describes the Entropy Reduction Engine, an architecture for the integration of planning, scheduling, and control. The architecture is motivated, presented, and analyzed in terms of its different components; namely, problem reduction, temporal projection, and situated control rule execution. Experience with this architecture has motivated the recent integration of learning, and this paper also describes the learning methods and their impact on architecture performance.

An architecture for knowledge-based graphical interfaces

Abstract: The construction of intelligent interfaces can be greatly facilitated by classifying the information that users and programs communicate, and by separating the user interface from the functionality of a program. This paper presents a scheme for classifying this information, and show how, by structuring the interface around this scheme, the user interface and functionality of a program can be separated, and tools can be built that provide assistance to both users and developers of user interfaces.

Software architecture analysis: a case study

Abstract: The Arch project is investigating methods and tools for understanding, specifying, controlling and improving the subsystem architecture of large so~are systems. This paper focuses on one of Arch’s capabilities, critiquing modularity. It discusses the relationship of modularity and architecture to configuration management, describes Arch’s information-sharing measure and its heuristic method, maverick analysis, for spotting poor information-hiding, and gives examples of using Arch tofind and analyze problem modules. Then it describes a case study in which Arch was used to analyze a “real”, production software system, including the real developer’s responses to Arch’s analysis.

A formal approach to security architectures

Abstract: We define a formal language whose symbols are security goals and mechanisms. This allows us to express every security architecture as a string. Designing a security architecture becomes the task of generating a word in the language. Analysing a security architecture becomes the task of parsing a string and determining if it belongs to the language. Since not every complete security architecture achieves its goals equally efficient, we associate a complexity parameter to every goal and mechanism. This allows us to identify complexity- reducing and complexity-increasing mechanisms.

Software architecture for a cell controller

Abstract: The primary objective of this study was to develop a versatile software architecture to integrate two NC machines, two robots, a vision station, and a conveyor based material transport system into a completely computer controlled manufacturing cell. Several home-built hardware/software interfaces were used in integrating the various manufacturing elements in this cell. The architecture of the cell control software is generic enough to be applicable to many small manufacturing facilities. From the system development perspective, the control software is a group of tasks working as a team in a multi-tasking environment. From the end user's perspective, it is a totally data-driven flexible manufacturing system. >

A knowledge exchange architecture for collaborative human-computer communication

Abstract: Based on accepted reference models of human and computer communication, a combined human-computer communication architecture is developed for exchanging knowledge. The architecture explicitly recognizes and prescribes a set of syntactic and semantic content functions needed to exchange knowledge for the achievement of collaborative problem solving. The functional components of this architecture are presented, and its potential for the development of more effective human-computer interaction is examined. >

Transaction security system extensions to the common cryptographic architecture

Abstract: A well-designed application program interface for a line of cryptographic products simplifies customer use of cryptographic services by helping to ensure compliance with national and international standards and by providing intuitive high-level services that may be implemented on disparate systems. The Common Cryptographic Architecture is IBM's strategic cryptographic architecture. The Transaction Security System implements the Common Cryptographic Architecture in full. Furthermore, the Transaction Security System has implemented extensions to the architecture to address additional customer requirements. This paper gives the design rationale for some of the additional cryptographic functionality in the Transaction Security System beyond that mandated by the Common Cryptographic Architecture.

A VLSI architecture for gray-scale morphological filtering and its application

Abstract: The authors propose a new VLSI architecture for morphological filtering. It reduces the need of arithmetic addition and subtraction by a simple logical candidate selection. Hardware complexity is simplified with pipeline operations. The word-parallel bit-pipeline architecture is suitable for high-speed processing while the bit-serial architecture is suitable for large structuring element. A bit-level systolic design is also demonstrated. This architecture can be applied to distance transformation. Fast real-time implementation is feasible through these concise architectures. >

ISO-OSI Security Architecture

Abstract: The Reference Model for Open Systems Interconnection (OSI-RM) enables two APs — residing on different end-systems — to exchange information with each other. In case the information exchanged is transmitted via public telecommunication lines, certain attacks can be envisaged.

Adding a man-machine interface to an architecture for mobile robots

Abstract: This paper describes a man/machine interface and its integration into a more general architecture for incompletely autonomous mobile robots. The architecture is composed of four levels, the functional level, the control level, the planner level, and the man/machine level. This architecture provides reactivity, execution monitoring and planning. Arguments are given to motivate the need for a man/machine interface for a mobile robot. With this interface, the operator has access to all of the levels of the architecture and this increases the robustness of the overall architecture. Some examples are given. >

Digital Neural Network Architecture and Implementation

Abstract: Digital implementations of neural networks represent a mature and well understood technology, which offers greater flexibility, scalability, and accuracy than the analog implementations. For example, using digital logic and memory it is quite easy to partition a large problem so that it can be solved by a smaller (in terms of hardware) implementation. Using the same logic and memory, a digital implementation can realize more than one network and combine the results in a hierarchical fashion to solve large problems. The main drawbacks of digital VLSI implementations are however their larger silicon area, relatively slower speed and the great cost of interconnecting processing units. These problems are addressed in this paper and solutions to alleviate them are proposed. First, the theoretical foundations for digital VLSI implementations are developed. Based on those, the design of digital systems is proposed that offer great speed and at the same time do not require a large number of interconnections.

A generalised approach to machine control

Abstract: The intrinsic complexity and variability of typical real time control problems makes a generalised approach to producing control systems difficult to specify. Due to a lack of standardisation, current machine controllers are usually extremely difficult to configure, support and integrate together in a generalised manner. These problems have severely hindered the development and subsequent application of advanced factory automation. The exploitation of advanced computer technology, particularly modern software methods can now enable a consistent machine control structure to be maintained for diverse applications of widely differing complexity. This thesis addresses the need for a major change in the design of machine control systems and proposes the use of a reference architecture which offers a consistent approach to the control of real time industrial operations. A broad based look at existing control systems focuses on the functiona,lity they currently offer in the control of various categories of industrial operations. A study of current manufacturing automation highlights the functional similarities between the control requirements of different industrial processes both in terms of their control structure and hierarchical communication requirements for factory integration. Given this commonality it is proposed that all industrial controllers should logically be based upon a common hardware independent architecture. A design methodology has been devised, termed Universal Machine Control (UMC) which enables individual machine controllers to be created (with functionality closely matched to their specific applications) whilst still maintaining common structural and communications features. This methodology aims to simplify the process of defining, programming and controlling systems built up from user defined mechanical hardware. A modular design framework or reference architecture for machine control has been derived which allows control systems to be modelled in a generalised manner. A particular implementation of the control architecture conforming to this reference model and an associated definition environment have been created. The implementation is based on the selective use of modern computer methods and emerging standards for real-time control. A demonstration system has been produced targeted at the flexible assembly of printed circuit boards. The possible application areas for this control philosophy are however extremely diverse and it could have a significant impact on automation methods.

Performance analysis through memory of a proposed parallel architecture for the efficient use of memory in image processing applications

Abstract: This paper presents an analytical method to measure the performance through memory of a proposedparallel processing computer architecture for image processing applications. We developed an analyticalmodel of our proposed architecture and a conventional architecture with respect to the system's local andmain memory to measure and compare the performances of these two systems. From our model we canevaluate the performance of the proposed architecture in terms of processor utilization, number of busy

The POOMA architecture

Abstract: This article contains an overview of the POOMA hardware architecture and its prototype implementation, as developed within the machine subproject of the PRISMA (PaRallel Inference and Storage MAchine) project The prime objective of the POOMA (Parallel Object Oriented MAchine) architecture is to support high performance database applications These applications are both data-intensive and processing-intensive Optimal support is achieved by using a large main memory in order to make access to large amounts of data very fast, and by using parallelism in order to obtain the required processing capacity The POOMA architecture is based on a network of computing ‘nodes’; each node consisting of a Data Processor, a memory and a Communication Processor This approach leads to a scalable multiprocessor with distributed memory, the network being the most novel part of the architecture Secondary storage in the form of disks is intended only for archiving purposes A 100-node prototype has been implemented and is currently in use for software implementation and experiments The implementation of the system, the nodes, the network, Communication Processor and the software environment for using the machine are described in some detail Some evaluation results and comparisons with other systems are presented, confirming the potential of the hardware architecture as such

An Analogue Neuron Suitable for a Data Frame Architecture

Abstract: This paper describes the VLSI realisation of a novel neural network implementation architecture which is geared to the processing of frame based data. The chief advantage of this architecture is its elimination of the need to implement total connectivity between neural units as hard-wired connections. This is achieved without sacrificing performance or functionality. A detailed description of the implementation of this architecture in 2μ CMOS, using a mixed analogue and digital building blocks is given together with details of system level design.