Showing papers on "Registered memory published in 1982"

The Prime Memory System for Array Access

Abstract: In this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation.

Self-configuring digital processor system with global system

Abstract: A digital processor system including several function modules where each module includes circuitry to perform at least one computational task and the circuitry to transfer information containing that modules respective computational task capability to a global memory upon initialization of each module and further circuitry to interface to the global memory upon initialization together with circuitry to interface to the global memory to determine each modules address. Further included is an information bus connected to the function modules and the to global memory. This system configuration allows for the system to self-configure upon power up intialization.

Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors

Abstract: In this paper we compare the effective bandwidth in a multiprocessor with shared memory using as interconnection networks the crossbar or the multiple-bus. We consider a system with N processors and N memory modules, in which the processor requests to the memory modules are independent and uniformly distributed random variables. We consider two cases: in the first the processor makes another request immediately after a memory service, and in the second there is some internal processing time.

Secure microprocessor/microcomputer with secured memory

Abstract: A digital processing device fabricated on a single semiconductor substrate includes an electrically programmable memory, a random access memory, a central processing unit, all connected by an information transfer bus. An external interface is provided connected to the information transfer bus to provide information contained on the bus to external devices. At least one security bit is provided to determine the status of data stored in the nonvolatile memory and portions of the random access memory. An external interface inhibit circuit is connected to the external interface. Address logic is connected to the information transfer bus to determine when information contained in the electrically programmable memory or the random access memory is being accessed. The address logic also determines the security status of information stored in the selected portions of the random access memory and the electrically programmable memory. In addition, the address logic is connected to the central processing unit to determine when an instruction operand is being fetched. The address logic is also connected to the external interface inhibit circuit to inhibit the operation of the external interface when an instruction operand is being fetched from the electrically programmable memory or selected portions of the random access memory.

Dynamic replacement of defective memory words

Abstract: A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply by providing a different address in the replacement page register.

Memory system with selective assignment of spare locations

Abstract: A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory (30). The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.

Remap method and apparatus for a memory system which uses partially good memory devices

Abstract: A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations. Thereafter, the microprocessor section interprets the "slice bit map" and assigns column addresses in the static memory locations designating locations within the defect-free memory. The assignment is carried out in a predetermined manner according to fault category to maximize the use of all of the groups of bit locations within each defect free memory location thereby making storage available for remapping new faults.

Bank switchable memory system

Abstract: A decoding circuit is coupled to the signal lines that communicate address signals to a memory unit. When a predetermined address is communicated, the decoding circuit produces a supplemental signal that is coupled to the memory unit and used to select one of a plurality of groups of memory locations. The communicated address signals specify the memory location of the selected group to be accessed.

Memory module selection and reconfiguration apparatus in a data processing system

Abstract: A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization. The central unit processes such information and provides memory, via a channel (30), with information representative of the capacity of the first modules (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory. This information is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory. When the memory is addressed, the most significant address portion (BA 03-06) is compared simultaneously by several comparators (33, 34, 35, 36), one for each register, with the content of the several registers. The result of the comparison from the comparators are applied to a decoder (37) which generates signals selecting one among the several memory modules.

Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory

Abstract: In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write The host processor passes an AGEOLD parameter to the memory subsystem and this parameter regulates the trickling of segments Unless the memory system is idle (no I/O activity), no trickling takes place until the age of the oldest written-to segment is at least as great as AGEOLD A command is generated for each segment to be trickled and the priority of execution assigned to such commands is variable and determined by the relationship of AGEOLD to the oldest age since first write of any of the segments If the subsystem receives no command from the host processor for a predetermined interval, AGEOLD is ignored and any written-to segment becomes a candidate for trickling

Hierarchial memory system with separate criteria for replacement and writeback without replacement

Abstract: In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to segments to the bulk memory without replacement is accomplished in accordance with an age since first write algorithm.

Memory cartridge for video game system

Abstract: A decoding circuit is coupled to the signal lines that communicate address signals to a memory unit. When a predetermined address is communicated, the decoding circuit produces a supplemental signal that is coupled to the memory unit and used to select one of a plurality of groups of memory locations. The communicated address signals specify the memory location of the selected group to be accessed.

A microcomputer with digital signal processing capability

Abstract: A single microcomputer for realtime digital signal processing and high-speed controller applications, with a 200ns instruction cycle, 16 × 16 parallel multiplier, 32b arithmetic unit, 144 by 16 data memory, a 1536 by 16 program and coefficient memory, will be discussed.

Memory system with automatic memory configuration

Abstract: A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.

Direct memory access logic system for a data transfer network

Abstract: A system provided within the Interface Circuit of a subsystem-controller for rapid and direct data transfer between the memory means of the subsystem controller and the main memory of a host computer or selected remote peripheral terminals.

Content-addressable memory module with associative clear

Abstract: A content-addressable memory module which performs an associative clear operation in response to a clear signal provided on a clear line. The associative clear operation simultaneously clears all registers in the content-addressable memory module whose contents match bits in a pattern input to the content-addressable memory module. A mask input along with the pattern determines which bits of the pattern are significant for the match. Each register in the content-addressable memory module has a bidirectional match line associated with it. A register's bidirectional match line carries a match signal only if that register contains data matching the pattern bits specified by the mask and the bidirectional match line is receiving a match signal from an external source. Clearing logic associated with each register clears the register when a clear signal appears on the clear line while the register's bidirectional match line is carrying a match signal. In content-addressable memories constructed of such content-addressable memory modules, memory match lines connect match lines associated with a number of registers. The memory match line and all of the match lines connected to it carry match signals only if each of the registers associated with the match lines contains data matching the pattern and mask input to the content-addressable memory module containing the register. The content-addressable memory module further contains logic allowing the use of encoded addresses to address individual registers in the content-addressable memory module.

Use of implant process for programming ROM type processor for encryption

Abstract: A digital processing system including a nonvolatile memory for the storage of instructions and data where the memory contains a plurality of field effect transistors which selectively conduct current according to the electrical state of their gates and the doping of their channel regions. Also included is a central processing unit for performing operations on data connected to an information transfer bus which is in turn connected to the nonvolatile memory. The information bus is additionally connected to an external interface circuit that provides interface to external peripherals. The memory is programmed by the doping of the channel regions instead of the fabrication or nonfabrication of the gates. Therefore, data that is stored in the memory is invisible to one examining the memory itself. This allows protection to software stored in the permanently programmed memory.

Hierarchical memories having two ports at each subordinate memory level

Abstract: A hierarchical memory system is disclosed comprising at least one dual-ported memory level, each port having access to a separate bidirectional data bus. The port facing the higher memory levels is equipped with a pair of data buffers having a bit width equal to the bit width of a single row of cells in the storage array contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The outer buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.

Control of serial memory

Abstract: A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.

Data processing system having branch instruction prefetching performance

Abstract: In a data processing system there are provided a main memory device for storing information, a plurality of buffer memory devices including a plurality of blocks for storing a copy of information stored in the main memory device, an arithmetic operation controller including at least one block corresponding to at least one of the blocks of the buffer memory devices for executing instructions including a branch instruction, a branch direction control memory device for storing branch direction information obtained by executing the branch instruction and a preceding controller. The preceding controller comprises a read out means for reading out from the buffer memory devices branch direction information together with a prefetched instruction predicting means for predicting whether a branching will be successful or not.

The concept and initial studies of a crosstie random access memory (CRAM)

Abstract: The crosstie‐Bloch line memory elements which were used in the serial crosstie memory can be reconfigured into a random access memory. The new approach decreases the access time, eliminates complexity, increases reliability, and is straightforward. The five‐level nonvolatile device is intended to be integrated on a silicon chip with decoders and drivers on the chip. It is expected that some of the five levels will be folded in with the levels used to connect the transistors needed for decoding and driving.

Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same

Abstract: An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.

Data prefetch apparatus

Abstract: A data prefetch apparatus provided between a main memory formed of a plurality of memory blocks and an I/O device whose data transfer speed is slower than that of the main memory, comprising an address counter for the main memory and a data buffer for storing the data prefetched from the main memory In the data prefetch apparatus, a full/empty detector is connected to the data buffer and a memory block detector is connected to the address counter and the data prefetch is interrupted when the over-access of the one of the memory block is detected and is restarted when the data buffer is empty and data request is supplied from the I/O device

Data processing machine suitable for high-speed processing

Abstract: A data processing machine for high speed processing especially of programs involving repeated executions of operational steps is disclosed, which comprises: A first memory for storing destination addresses of data; a second memory being accessed with the destination addresses output from said first memory and storing instructions therein; a third memory for receiving the data and holding it therein temporarily; a fourth memory allowing the data sent from said third memory to wait for another; an arithmetic means executing arithmetic operation in accordance with the instructions read out from said second memory; a bus for coupling said first memory, second memory, third memory, fourth memory and said arithmetic means into a ring shape; and a means for storing the destination addresses and the instruction transferred from the outside into said first and second memories, respectively. By this structure the arithmetic means and the first to fourth memories are formed in a pipe line mode, the instructions input through the interface part are stored in the second memory, and arithmetic processing for data flowing through the ringshaped bus is executed in the arithmetic means in accordance with instructions which are fetched from the second memory. The sequence of operations in the pipe line mode can be programmably controlled in accordance with the arranged instructions in the second memory.

Digital tester local memory data storage system

Abstract: In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the data channel. In addition, a transition bit is stored in each memory location to signify whether the vector information in that location represents valid transition data. The transition bit is used to control the reading of information from the memory into a register that controls the flow of information in the data channel, so that only the valid transition vectors are fed into data channel control circuitry. This procedure substantially reduces the amount of data that must be loaded into the memory, and hence reduces the total time necessary to thoroughly test a circuit.

Dynamic random access memory having separated VDD pads for improved burn-in

Abstract: A random access memory, a method of manufacturing a random access memory, and a method of testing a random access memory in which separate operating voltage terminal pads are provided for the memory cell arrays and peripheral circuits of the memory. By providing separate operating voltage terminal pads, different operating voltages can be applied to the array of cells and the peripheral circuits during a burn-in procedure. In this manner, the burn-in procedure is greatly accelerated without danger of damage to the peripheral circuits due to exceeding the sustaining voltages of the transistor devices of the peripheral circuits during burn-in.

FIFO Memory device

Abstract: A first-in-first-out memory device which is operable at a high-speed is disclosed. The memory device comprises a plural stages of memory units and a plural stages of control unit, each of the control units including a circuit for indicating whether its stage holds effective data or not, a circuit for receiving a signal of the indicating means of the previous stage, and a circuit generating a write signal when the memory cell holds no effective data and the previous stage hold effective data, in which the write signal is used to remove data stored in the previous memory cell to the corresponding stage memory cell.

Method and system to recognize change in the storage characteristics of a programmable memory

Abstract: To recognize change in the storage characteristics of programmable memory elements, particularly EPROMs, the memory content of an addressed memory element or cell is read out, the first time, at normal design voltage level; the data so read are then again read out at a changed voltage level, for example at a higher or lower read-out voltage, or higher or lower operating voltage of the EPROM, and compared. If the data do not match, the particular memory cell will have the tendency to become defective due to loss or accumulation of charge carriers in due course although, for some time yet, the specific memory cell will function satisfactorily. Detection of errors upon operation under changed voltage conditions provides early warning of failure of a cell.

Circuit for allocating memory cycles to two processors that share memory

Abstract: A circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures. In one procedure, control of memory is transferred only after a request for memory access has been made. In a second procedure, transfer of memory control to a requesting processor is automatically accompanied by a request to return control. The control memory of a processor selects the process by two bits called Code Idle and Code Release. Code Idle accompanies instructions that usually mean that the releasing processor will not need memory for several memory cycle times, and an explicit request for transfer is made when memory is actually needed. Code Release accompanies instructions that do not require memory access at the time but are typically followed by a memory request within a processor cycle time or a few processor cycle times. Memory control is returned without the delay that is associated with an explicit request.