Showing papers on "Static induction transistor published in 1985"

The δ-Doped Field-Effect Transistor

Abstract: A new Schottky-gate FET grown by molecular-beam epitaxy is presented. A V-shaped potential well with a 2D electron-gas is generated in the epi-layer by implementation of a δ-function like doping profile. The δ-doped FET is scaled down to its ultimate physical limit normal to the crystal surface. The advantages of the new device are high gate-breakdown voltage, high transconductance due to the proximity of the electron channel to the crystal surface, and high electron concentration in the channel. Current-voltage and capacitance-voltage measurements reveal a large breakdown voltage and a narrow impurity and carrier distribution.

The bipolar inversion channel field-effect transistor (BICFET)—A new field-effect solid-state device: Theory and structures

Abstract: A new solid-state field-effect bipolar device designated the BICFET for bipolar inversion channel field-effect transistor is proposed. The device, which is bipolar in nature and relies upon the field-effect inducement of an inversion layer, that corresponds to the conventional neutral base of a bipolar transistor, features potentially very high current gain (105), very high current operation (106A/cm2) and thus high transconductance (4 × 107S/cm2) and low input capacitance. The BICFET has three terminals: a metallic emitter which makes ohmic contact to a semi-insulator (wide bandgap semiconductor); a source terminal which contacts an inversion layer formed at the interface between the semi-insulator and the semiconductor depletion region; and a collector which is the semiconductor bulk. An important feature of this bipolar device is the absence of the base layer and all of its associated problems. The principle of operation is based on controlling the flow of majority carriers through the semi-insulating region to the collector by the biasing action of charge in the inversion channel. A significant advantage of the BICFET structure is that it is not subject to the scaling limitations due to punchthrough as in the MOS or junction bipolar transistor. The problem of threshold control in the MOS transistor is avoided, so the requirement of very shallow junctions may be relaxed.

Temperature behavior of insulated gate transistor characteristics

Abstract: The Insulated Gate Transistor (IGT) is a new power semiconductor device with the high input impedance features of the power MOSFET and the ability to operate at high current densities even exceeding that of power bipolar transistors. The high temperature operating characteristics of the device are discussed here. Unlike the power MOSFET whose operating current density decreases by over a factor of 2 when the ambient temperature is raised to 150°C, the IGT is found to maintain its high operating current density at elevated temperatures. The temperature coefficient of the output current is found to be positive at forward drops below 1.5 V and negative at forward drops above 1.5 V. These characteristics make the IGT suitable for applications with high ambient temperatures. The results also indicate that these devices can be paralleled without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.5 V.

A new superconducting-base transistor

Abstract: The continuing search for a good cryogenic transistor has led to a new proposal, the superconducting-base semiconductor-isolated transistor (SUB-SIT). This three-terminal device is expected to have characteristics very similar to those of bipolar transistors, but at millivolt operating levels. We present discussions of the concepts involved in the SUBSIT, proposed fabrication techniques, and theoretical results for its DC and high frequency characteristics.

Strained-quantum-well, modulation-doped, field-effect transistor

Abstract: A new modulation-doped field-effect transistor structure which employs a thin (8 nm) strained layer of In 025 Ga 075 As as the channel is described The prototype device with a 29 μm gate length had a peak, room-temperature, unilluminated extrinsic transconductance of 91 mS/mm (VDS = 1 V) If device performance scaled linearly with gate length to 1 μm, as do (Al, Ga)As/GaAs, single-interface, modulation-doped FETs, this is the best room-temperature performance reported to date for an (In, Ga)As channel, modulation-doped transistor Furthermore, the transconductance of the strained-quantum-well transistor proved to be almost constant with gate voltage, varying less than 13% over a 05 V range at 77 K This will allow the fabrication of extremely linear microwave amplifiers and supports the assertion that the current conduction path is the (In, Ga)As channel

MOS current limiting output circuit

Abstract: An MOS current limit circuit which provides current limiting protection is provided. A driver transistor of a conventional output stage is coupled to a current limiting transistor which is one transistor of a current mirror. The current limiting transistor of the current mirror has the V GS thereof accurately biased to insure a precise current limit value. When the current limiting transistor is not performing a current limiting function, the current limiting transistor is made conductive and further provides high voltage protection to the driver transistor when the driver transistor is nonconductive.

Static induction transistors optimized for high-voltage operation and high microwave power output

Abstract: An optimized static induction transistor (SIT) design utilizing local oxidation in a self-aligned geometry is described. Devices with 10.5- and 7-µm pitch (gate-to-gate spacing), which have been optimized with respect to epitaxial layer thickness and resistivity, have attained a combination of operating frequency and breakdown voltage which is much higher than devices made with other technologies. The 10.5-µm pitch SIT's have a blocking voltage of 170 V with 6-dB gain at 225 MHz and 10-dB gain at 900 MHz. Typical multicell power devices have demonstrated 110-W output power at 225 MHz with 65-percent drain efficiency and 25 W at 900 MHz with 40-percent drain efficiency, operated at voltages in excess of 100 V de bias. The 7-µm pitch SIT's have a blocking voltage of 140 V and the same power gain performance at 225 and 900 MHz as the 10.5-µm pitch devices, but with higher effiency and a higher maximum frequency of operation. Typical multicell power devices of this type have achieve 110-W output power at 225 MHz with 70-percent drain efficiency and 25 W at 900 MHz with 55-percent drain efficiency operated at 90 V de bias.

Comparison of lateral and vertical DMOS specific on-resistance

Abstract: The specific on-resistance characteristics of the lateral and vertical DMOS transistors are compared for voltages between 50 and 800 volts. The vertical DMOS transistor's breakdown and on-resistance relationship is reviewed, followed by modeling results of the lateral DMOS transistor's breakdown and on-resistance characteristics. A direct comparison is then made between the vertical and lateral devices. The results indicate that the vertical device has lower specific on-resistance at low voltages because of its higher channel width/unit chip area packing. At higher voltages, the lateral device becomes equal to or better than the vertical device because of its ability to maintain a high drift region conductivity.

Effective base resistance of bipolar transistors

Abstract: Two formulations, one appropriate for dc analysis and the other for low-frequency ac analysis, are developed to calculate effective lumped base resistance of bipolar junction transistors. These formulations are defined in terms of terminal characteristics, and are more appropriate for device behavior in circuit modeling applications than those formulations currently in the literature. This is most apparent at high current levels, where appreciable current crowding is present and all of the models under consideration give markedly different results. The present calculations are made for a discrete transistor of single base-stripe geometry, but the results are applicable to integrated-circuit transistors and can be readily extended to other geometries.

Modeling the turn-off characteristics of the bipolar-MOS transistor

Abstract: Since the turn-off speed of the new bipolar-MOS power transistor is slow compared to that of a MOSFET, it is important to understand the limiting mechanism and the prospect for future improvement. In this letter, it is demonstrated that the turnoff waveform can be explained by a model based on a simple equivalent circuit and the transistor open-base turn-off process. The model is applied to explore the impact of some process modifications on speed improvement and to study the tradeoff between speed and on-resistance.

Power supply having dual ramp control circuit

Abstract: A power supply (100) includes a first lead (12) for receiving an input voltage (Vin) and an inductor (L1) and a switching transistor (Q1) coupled in series between the input lead and ground. The node (N1) between the inductor (L1) and switching transistor (Q1) is coupled through a diode (D1) to an output terminal (14). When the switching transistor is on current flow causes energy to be stored in the inductor. When the switching transistor turns off, the energy stored in the inductor is provided to a load (RL) coupled to the output terminal. The on-time of the transistor is controlled by a comparator (20) which receives a first voltage (V3) proportional to the current through the switching transistor and a second voltage (V4). The second voltage decreases linearly with respect to time at a rate dependent on the difference between the voltage at the output terminal (Vout) and a reference voltage (Vref). Because of this, the power supply is insensitive to voltage spikes which may appear on the first input lead of the comparator.

Bidirectional output semiconductor field effect transistor

Abstract: A high voltage bidirectional output semiconductor field effect transistor (BOSFET) is disclosed which is turned on from the electrical output of a photovoltaic stack which is energized from an LED. The process for manufacture of the device is also disclosed. The BOSFET device consists of two lateral field effect transistors formed in an implanted N(-) region in a P(-) substrate. Two spaced drain regions feed inwardly toward a common N(+) source region separated from the drains by respective P type diffusions. The surface of these diffusions can be inverted by application of voltage to the suitably disposed gate electrode. The depletion field between channel and drain regions is well controlled over the surface of the device. The source contact remains close to the potential of the gate contact at all times so that the device can be used for high voltage switching of either polarity. A diode, PNP transistor and resistor are integrated into the same chip containing the lateral BOSFET device to form a solid state relay circuit having characteristics similar to a reed relay. The diode defines a forward conduction path from a photovoltaic pile voltage source directly to the BOSFET gate so that the BOSFET gate capacitance can be quickly charged during turn-on. The PNP transistor is a high gain transistor coupled to the diode and to the input resistance of the circuit. The input impedance of the circuit is reduced by the gain of the transistor when the photovoltaic output voltage is turned off and its voltage drops to below the gate voltage by about 0.6 volt to turn on the transistor. This allows the BOSFET to quickly turn off as though the circuit had a relatively low input impedance. The integrated control circuit with diode and transistor are electrically isolated from the field effect transistor in the chip by inner and outer isolation diffusions with an isolation moat therebetween. Another control circuit is disclosed which employs a dV/dt suppression clamp circuit and a regenerative turn-off circuit.

Electronic proximity switch device

Abstract: An electronic switch of the type having two external lines, one of which is connected to one pole of an operating voltage source in series with a load and the other of which is connected with the load. The switch comprises a sensor, e.g. an oscillator, responsive to proximity of an object thereto and has an output transistor operated by the sensor with blocking and conductive states selectively controlled by the transistor in response to the oscillator. A MOS-FET power transistor is in series with the output transistor and, to reduce the voltage drop in a conducting state of the electronic switch, a self-conducting MOS-FET is used as the MOS-FET power transistor.

Field-theoretic analysis of wave propagation on FET electrodes including losses and small-signal amplification

Abstract: A wave-theoretic analysis of MESFET electrode structures is presented where for the first time both the losses caused by the semiconductor layer and those caused by the finite conductivity of the electrodes are taken into consideration. The active properties of the transistor are modelled by adopting a suitable small-signal theory. The results are discussed by taking as an example a TW FET design, although they are equally relevant for all standard microwave MESFETs.

Light quenchable thyristor device

Abstract: A thyristor device comprising an SI (Static induction) thyristor or beam base thyristor and an SIT (static induction transistor) or SIT-mode bipolar transistor connected to the gate of the thyristor in order to make it possible to turn-on and-off a direct current and voltage at a high speed with a light. In the thyristor part, the SIT gate structure or SIT-mode beam base structure exists in the first gate or base region or second gate or base region so that, at the time of the triggering operation, a very high switching efficiency will be obtained.

Semiconductor memory device having improved data output circuit

Abstract: A semiconductor memory device is disclosed in which an output data voltage of a sense amplifier is compared with a reference voltage to produce an output data corresponding to the data stored in the selected memory cell. The reference voltage is generated in response to a current flowing through a dummy memory transistor having the same device structure as a memory transistor and is thus variable if the current flowing through the memory transistor is deviated from the designed value.

Velocity saturation effect on short-channel MOS transistor capacitance

Abstract: To analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree quite well. Several causes of short-channel effects are explained by the simulations. Velocity saturation effects are found to play a key role in the gradual increase in C gd . Also holes in the accumulation region and the two-dimensional effect or the influence of the back-gate field from the drain are important in explaining the short-channel effect of MOS transistor capacitance.

Single-ended, self-oscillating DC-DC converter for intermittently energized load having VBE responsive current limit circuit

Abstract: The converter delivers current to an intermittently energized load and includes a coupled inductor having a primary winding, a secondary winding and a feedback winding. A switching transistor is coupled in series with the primary winding of the inductor and switches between conductive and non-conductive states to control the flow of current through the primary winding. A positive drive circuit provides positive bias voltage to the switching transistor. A current limiting circuit senses the voltage across the base-emitter junction of the switching transistor to measure the primary winding current, removes the positive bias voltage when the primary winding current reaches a predetermined value, and thereby switches the transistor out of the conductive state into the non-conductive state. A semiconductor switch includes a control lead coupled to a voltage divider which applies a scaled voltage to the control lead causing the semiconductor switch to conduct when the switching transistor base-emitter voltage reaches a predetermined current limit voltage representative of a preselected switching transistor collector current limit. The semiconductor switch then shunts the positive bias voltage away from the switching transistor base and switches that transistor into the non-conductive state.

Solid state image sensor including static induction transistor with gate surrounding source and/or drain

Abstract: A disclosed solid state image pick-up element is constructed by a lateral static induction transistor in which source and drain regions thereof are arranged in a surface of a semiconductor layer formed on a substrate and a gate region for storing a light charge completely surrounds at least one of the source region and the drain region, whereby a source-drain current flows in parallel with the surface of the semiconductor layer. Moreover, a disclosed solid state image sensor utilizing the solid state image pick-up element mentioned above further includes a biasing means for inversely biasing the source and drain regions during a light signal storing period.

High speed eprom cell and array

Abstract: A high speed EPROM cell comprises two floating gate field effect transistors and one field effect transistor. One of the floating gate transistors is smaller than the other floating gate transistor and functions as a programming transistor in developing charge on the interconnected floating gates. The larger dimensions of the other floating gate transistor allows increased read current and operating speed. The field effect transistor connects the larger floating gate transistor to a read drain terminal. The cell is readily fabricated using two doped polycrystalline semiconductor lines and two metallization lines in accordance with conventional semiconductor processing techniques.

Trapezoidal-groove Schottky-gate vertical-channel GaAs FET (GaAs static induction transistor)

Abstract: This letter reports, the development of a vertical-channel. GaAs FET with the unsaturated I-V characteristics of the static induction transistor (SIT) and voltage blocking capability up to 100 V. The device structure utilizes the anisotropic etching properties of GaAs, in which the gate regions are formed by a double-angle evaporation into trapezoidal etched grooves. This single evaporation step simultaneously provides both source and gate metallization, and the novel trapezoidal groove geometry automatically yields a self-aligned gate with separation of source and gate onto different levels, thus eliminating the need for critical alignment arising from source-gate interdigitation.

Excess energy protection device

Abstract: A device for protecting semiconductor devices during excess energy events. The device uses p-MOS field effect transistors in a common n-well with a common gate configuration. An input is coupled to the source of a first p-type transistor and to the n-well. The first transistor is coupled through a series resistor to a second p-MOS transistor. The drains of each transistor are coupled to ground and gate aided breakdown reduces the voltage at which breakdown occurs.

On state modeling of power JFET structures in the bipolar mode

Abstract: An analytical model for the on-state operation of the bipolar-mode power JFET is proposed. A closed-form solution in the low-voltage rnage of the output characteristics is obtained as a function of device parameters. The model shows that the hole-reflecting properties of the high-low drain transition are very important in order to achieve a lower on-state voltage drop. This allows us to explain the presence of an offset voltage in the output characteristics due to the recombination velocity effect at this transition. The effects of device parameters on the on-state operation, such as epi-thickness, lifetime and extent of heavy doping of source and drain are analyzed in detail and found in good agreement with experimental results.

Integrated circuit amplifier module

Abstract: A four-terminal integrated circuit high-frequency RF amplifier connects to external circuitry via a ground terminal, and RF input terminal, an RF output terminal and a DC biasing terminal. A two stage amplification architecture is employed--a current gain transistor (common-emitter) is cascoded with a subsequent voltage gain transistor (common-base) while yet maintaining RF signal inversion overall from input to output so as to increase stability. A biasing current-mirror transistor provides biasing current to the current-gain transistor. A fourth transistor connected as a forward-biased collector-base shorted diode between the current mirror biasing transistor and a common external biasing terminal supplies bias current to the current-mirror biasing transistor while simultaneously minimizing voltage swings across the current-gain transistor. The amplifier module has very low input capacitance which does not change appreciably with changes in load impedance, and operates with great stability under a wide range of different input and output conditions and RF frequencies. Because of its relative simplicity and compactness, the amplifier can be used to great advantage as an IC "building block" in a variety of different applications.

Insulated gate transistor array

Abstract: An insulated gate transistor (70) modified to increase its latching current density. On one side of gate (22), a high conductivity collector well (76) is provided to divert current which would otherwise flow through collector well (24) in a critical path (50) along source-collector junction (27), tending to forward bias the junction and cause the transistor to latch.

Overcurrent protection circuit for line circuits in a switching system

Abstract: An overcurrent protection circuit including a first transistor, a second transistor, and an integrator. The first transistor operates to control a current flow from a power source to a load. The second transistor is turned on when an overcurrent flows through the first transistor. The overcurrent is detected by watching the collector-emitter voltage of the first transistor. Thus, the second transistor operates to bypass the base current to be supplied to the first transistor with a certain delay time defined by a delay part, which enables an instantaneous overcurrent to be ignored.

Biasing circuit for a field effect transistor

Abstract: A circuit for biasing a field effect transistor using two voltages. With said circuit, the bias point of the transistor may be varied by varying the source bias voltage. At least one access electrode is polarized from a bias voltage through a first secondary transistor operating as saturable load. The gate of the main transistor and the gate of the saturable load are connected at two points of a divider bridge, supplied by the two bias voltages and comprising at least two resistors and a second secondary transistor. The gate-source voltage of said saturable load follows the gate-source voltage of said main transistor.

Power transistor thermal shutdown circuit

Abstract: A thermal shutdown circuit for use with a high power transistor which incorporates a sense emitter. A differential amplifier is driven from the transistor base and the sense emitter and has an output that is coupled to the power transistor base. When the sense emitter potential exceeds the base potential, the amplifier output will pull the base down so as to limit the current in the power transistor. For a silicon transistor, the circuit will act to limit the hottest portion of the sense emitter to a maximum of about 250° C. When there are no hot spots and the sense emitter is heated uniformly, heating of the transistor will be limited to about 200° C.

Emitter coupled logic circuit with high drivability for capacitive load

Abstract: An ECL (Emitter Coupled Logic) circuit is provided which has an increased ability to drive a large capacitive load or to drive a large fan-out circuit, wherein the power consumption per gate is reduced. The output circuit of the ECL circuit is provided with an emitter follower transistor which has the current therethrough detected by a detecting transistor. A current control transistor is provided to quickly charge the load capacitance under the control of the detecting transistor, and thus, the voltage drop of the output signal is improved. One of the emitter follower transistor and the current transistor are always cut off when the other is in a conductive state, and therefore, the current running through the circuit is reduced.

Overcurrent protecting circuit

Abstract: A transistor connecting a power source such as a battery to a load has its collector-emitter voltage monitored by a second transistor via a delay circuit such that the second transistor is turned on after a set delay following a change of the collectoremitter voltage. The second transistor is connected to the first transistor so that when turned on, it bypasses the base current to the first transistor to turn it off.