Proceedings ArticleDOI
Comparison of lateral and vertical DMOS specific on-resistance
M. Amato,V. Rumennik +1 more
- Vol. 31, pp 736-739
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TLDR
In this paper, specific on-resistance characteristics of the lateral and vertical DMOS transistors are compared for voltages between 50 and 800 volts, and the results indicate that the vertical device has lower specific onresistance at low voltages because of its higher channel width/unit chip area packing.Abstract:
The specific on-resistance characteristics of the lateral and vertical DMOS transistors are compared for voltages between 50 and 800 volts. The vertical DMOS transistor's breakdown and on-resistance relationship is reviewed, followed by modeling results of the lateral DMOS transistor's breakdown and on-resistance characteristics. A direct comparison is then made between the vertical and lateral devices. The results indicate that the vertical device has lower specific on-resistance at low voltages because of its higher channel width/unit chip area packing. At higher voltages, the lateral device becomes equal to or better than the vertical device because of its ability to maintain a high drift region conductivity.read more
Citations
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Journal ArticleDOI
3.8-MV/cm Breakdown Strength of MOVPE-Grown Sn-Doped $\beta $ -Ga 2 O 3 MOSFETs
Andrew J. Green,Kelson D. Chabak,Eric R. Heller,Robert C. Fitch,M. Baldini,Andreas Fiedler,Klaus Irmscher,Günter Wagner,Zbigniew Galazka,Stephen E. Tetlak,Antonio Crespo,Kevin D. Leedy,Gregg H. Jessen +12 more
TL;DR: In this article, a Sn-doped (100) $\beta $ -Ga2O3 epitaxial layer was grown via metal-organic vapor phase epitaxy onto a single-crystal, Mg-Doped semi-insulating (100, β)-Ga 2O3 substrate.
Proceedings ArticleDOI
A review of RESURF technology
TL;DR: The reduced surface field (RESURF) technology is one of the most widely used methods for the design of lateral high-voltage, low on-resistance devices as mentioned in this paper.
Journal ArticleDOI
New thin-film power MOSFETs with a buried oxide double step structure
Baoxing Duan,Bo Zhang,Zhaoji Li +2 more
TL;DR: In this paper, a new silicon-on-insulator (SOI) power MOSFET structure is proposed, in which buried oxide step structure (BOSS) is replaced by a buried oxide double step (BODS).
Journal ArticleDOI
New Superjunction LDMOS With $N$ -Type Charges' Compensation Layer
TL;DR: In this paper, a new superjunction lateral double diffused MOSFET (LDMOST) was designed with an N-type buried layer in the P-substrate near the drain to suppress the effect of substrate-assisted depletion resulting from the imbalance between the pillars of the super junction layer.
Patent
Semiconductor device having improved power density
TL;DR: In this paper, an MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivities type formed in the semiconductor layers proximate an upper surface of the semiconductors.
References
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Proceedings ArticleDOI
High voltage thin layer devices (RESURF devices)
J.A. Appels,H.M.J. Vaes +1 more
TL;DR: The RESURF (Reduced SURface Field) as discussed by the authors is a diode-based diode structure for high voltage devices with very thin epitaxial or implanted layers, where crucial changes in the electric field distribution occur at or at least near the surface.
Journal ArticleDOI
Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors
S.C. Sun,James D. Plummer +1 more
TL;DR: Structural differences which result in on-resistance and transconductance differences between the devices are described and quantitative models, suitable for device design, are developed for the on-Resistance of each type of structure.
Journal ArticleDOI
Effects of drift region parameters on the static properties of power LDMOST
TL;DR: In this paper, the effects of drift region geometry and the physical parameters on the thin layer (resurfed) lateral DMOS transistor operation have been studied for both the static on-state and the off-state.
Proceedings ArticleDOI
Optimum design of power MOSFETs
P.L. Hower,T.M.S. Heng,C. Huang +2 more
TL;DR: In this article, three cell geometries (rectangle, square and hexagon) have been investigated using a lumped R ds model and it is demonstrated that for each geometry one can calculate a spacing of the p-well diffusions that minimizes R Ds.
Proceedings ArticleDOI
Design of high-density power lateral DMOS transistors
TL;DR: In this paper, a significant reduction in the surface area required for high voltage lateral DMOS transistors (LDMOSTs) has been achieved by applying a field shaping technique, resulting in transistors exhibiting breakdown voltages well in excess of the planar junction limit.