Showing papers on "Stuck-at fault published in 1989"

Failure diagnosis of structured VLSI

Abstract: The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure. Diagnosis consists of simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel. The method is also suitable for signature-based random-pattern testing. The authors discuss diagnostic fault simulation, fault-list generation, relating faults to defects, diagnostic strategy, and random-pattern failures, and they report some experimental results to indicate the procedure's power. >

A directed search method for test generation using a concurrent simulator

Abstract: A description is given of the application of a concurrent fault simulator to automatic test vector generation. As faults are simulated in the fault simulator a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. Experimental results are presented showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, it has been possible to generate: (1) initialization sequences; (2) tests for a group of faults; and (3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach. >

Efficient generation of test patterns using Boolean difference

Abstract: Most automatic test pattern generation systems for combinational circuits generate a test for a given fault by directly searching a data structure representing the circuit to be tested. The author describes a novel system that divides the problem into two parts: first it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. The novel system can incorporate any of the heuristics used by structural search techniques. It is not only quite general but is able to test or improve untestable every fault in the popular Brglez-Fujiwara test benchmark (Int. Symp. Circuits and Systems, June 1985). Experimental results are presented. >

Fast test generation for sequential circuits

Abstract: An efficient sequential circuit test generation algorithm is presented. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of an initial time-frame algorithm and correct implementation of a solution to the previous state information problem. The initial time-frame algorithm determines the number of time-frames required to excite the fault under test and the number of time-frames required to observe the excited fault. This step saves the test generator from doing unnecessary search in the input space. Test generation is done strictly in forward time. The algorithm saves good machine circuit state after test generation to aid in future test generation. Faulty machine state is set to unknown whenever test generation for a fault is begun. This solves the previous state information problem, which has often been ignored by existing test generators. >

Parallel Pattern Fault Simulation of Path Delay Faults

Abstract: This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

Layout-driven test generation

Abstract: Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n). >

Fault partitioning issues in an integrated parallel test generation/fault simulation environment

Abstract: The authors address the issues involved in providing an integrated test generation/fault simulation environment on a parallel processor. They propose heuristics to partition faults for parallel test generation with minimization of the overall run time and test length as an objective. For efficient utilization of available processors, the work load has to be balanced at all times. Since it is very difficult to predict a priori how difficult it is to generate a test for a particular fault, the authors propose a load-balancing method which uses static partitioning initially and then dynamic allocation of work for processors which become idle. They present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits. The main contribution of the work described is to show that if one is not careful in the design of a parallel algorithm, apart from inefficient utilization of available processors, degradation in the quality of solutions can occur. >

CrossCheck: A Cell Based VLSI Testability Solution

Abstract: A new testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs. The test points are accessed through an on-chip grid of orthogonal probe and sense lines. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. The sizable number of test points improves the testability of the designs by a very large factor. Additionally, analog measurement and signal injection capabilities allow detection of practical CMOS fault modes such as opens, shorts, open or closed FETs and even noise margins. The large observability of CrossCheck based designs reduces the automatic test pattern generation problem to one of providing control only. Several ISCAS benchmark designs are analyzed using CrossCheck cell libraries and fault models. The results show that over 97 percent coverage of a broad range of fault modes, such as opens and shorts, can be obtained on VLSI CMOS designs without the need for large computing resources.

Simulation of spatial fault distributions for integrated circuit yield estimations

Abstract: Two methods used in fault simulation for integrated circuit modeling are described. Both methods simulate clustered fault locations on a map. In the first approach, the clusters are initially generated using a radial Gaussian probability distribution. The results are consequently passed through cluster shaping programs, which produce clusters that resemble those observed on actual integrated circuit wafers. In the second approach, faults are added to the chips as a function of time. The probability that additional faults are created during any interval of time is assumed to be related to the number of faults already on the chip, as well as the number of faults on adjacent chips. This technique generates frequency distributions of the number of faults per chip that closely resemble those observed in actual integrated circuits. >

On the computation of the ranges of detected delay fault sizes

Abstract: Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible Results of experiments performed to evaluate the practical benefits of the proposed methods are reported >

A statistical model for delay-fault testing

Abstract: The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test effectiveness in terms of the propagation delay of the path to be tested, the size of the delay defect, and the system clock interval, and then combines the data for all delay faults to measure total delay-fault coverage. The authors also propose a model for measuring the defect level as a function of the manufacturing yield and the predictions of the statistical delay-fault coverage model. >

Fault diagnosis in analogue circuits using AI techniques

Abstract: The authors describe a technique for detecting and locating faults in analogue circuits by checking that the measurements are consistent with the circuit function. The unique representation used accommodates the imprecise nature of analogue circuits. A model of the circuit is formed from the constraints imposed by the behavior of the components and the interconnections. The values of parameters within the circuit are deduced by propagating the effects of measurements through this model. Faults are implied from the detection of inconsistencies and located by suspending constraints within the model. The method does not use fault simulation and is therefore applicable to any type of fault. It is able to detect performance variations, as well as catastrophic failures. Values are represented as ranges within which the true value lies. This overcomes the difficulty of representing the uncertainty inherent in any analogue design or measurements. The method has been successfully used to detect and locate a number of faults in several circuits. >

A test generation system for path delay faults

Abstract: A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the number of lines in the network, criteria and efficient algorithms to prune the number of paths for test generation are presented. The test generation system is evaluated using the ISCAS combinational benchmark circuits. >

Unpredictable fault detection using adaptive inference testing techniques

Abstract: A method of using an adaptive inference system to detect and locate faults in an electrical or electronic device or assembly. A position-dependent, time-ordered test is performed upon the device or assembly to provide a comprehensive error analysis. The error analysis includes an array of error data and information that is time interdependent. Once fault data is stored in memory, a newly-detected fault can be compared with the stored faults. A relationship between the stored fault data and the detected fault is determined. The system indicates the cause of the detected fault to the operator based on stored fault data that is most probably related to the detected fault. Possibilites of faults within the device or assembly are then displayed. This system analysis and range of potential causes can be evaluated by an operator. In this manner, faults not having been contemplated by stored data and information in the adaptive inference system and not bearing a direct relationship to a problem being reviewed can be identified.

Optimal granularity of test generation in a distributed system

Abstract: The problem of test generation for logic circuits is known to be NP-hard, and hence it is very hard to speed up the test generation process due to its backtracking mechanism. The authors present an approach to parallel processing of test generation for logic circuits in a loosely coupled distributed network of general-purpose computers. They analyze the effects of the allocation of target faults to processors, the optimal granularity (grain size of target faults), and the speedup ratio of the multiple-processor system to a single-processor system. To analyze the case in which a test pattern generated for one fault can also be a test pattern for other faults if fault simulation is performed, they introduce a ratio of newly processed faults to target faults and derive the expressions of optimal granularity in cases of both static and dynamic task allocation. They also derive an expression of the speedup of a multiple-processor system in the homogeneous case. The analysis indicates that the speedup approaches N, the number of servers, if the data transfer time per fault and the waiting time per communication are much smaller than the processing time per fault and if the decrease ratio of newly processed faults due to overlapped processing is much smaller than the ratio of newly processed faults. >

The parallel-test-detect fault simulation algorithm

Abstract: It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation. Several techniques for implementing a parallel-test-detect simulator are presented, with techniques based on nominator analysis providing the fastest fault simulation results. The dominant-test-detect approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might be used in built-in self-test. >

Experimental evaluation of testability measures for test generation (logic circuits)

Abstract: The results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms are presented. Each measure was evaluated using over 60000 faults in circuits of varying size and complexity. The performance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The results indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable. >

A Simplified Six-Waveform Type Method for Delay Fault Testing

Abstract: A new, simplified waveform method is presented for delay fault testing. The method enables accurate calculation of a delay fault detection threshold for definitely detectable faults, and a delay fault range for possibly detectable faults. The method is shown to correctly classify definitely detectable faults which are mis-classified by methods recently reported elsewhere [1] [2]. A quantitative delay fault model with variable fault size is used, and the effect of the delay fault is explicitly described by the new waveform method. The calculation of the detectable delay size threshold occurs in linear time for any definitely detectable fault.

High impedance fault detection for industrial power systems

Abstract: The authors describe the characteristics of high-impedance faults and the most effective techniques for detecting them. The benefits of high-impedance fault detection for industrial power systems are identified. It is shown that the most effective high-impedance-fault detection system incorporates several algorithms and monitors a number of parameters to ensure sensitivity and correct operation. Operating the detector in an alarm mode improves safety and fault location with minimal effect on service continuity. A valuable use for such a detector would be the identification of incipient faults, so that critical loads can be switched to another source before the fault becomes bolted and requires the circuit to be cleared. Using a detector in this way could save substantial down-time costs for critical processes. >

Transient and intermittent fault insertion

Abstract: Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) (10) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic (24) on such integrated circuit (10). Specific fault types programmable for each fault class include a stuck-open fault and bridging faults both wired-AND and wired-OR. The programmable fault insertion circuitry on each integrated circuit interfaces directly or indirectly with a BIT maintenance controller (12). In addition to verifying test software, a fault tolerant system's error detection and recovery circuits may be verified by fault insertion testing using the transient and intermittent fault insertions. The controller (12) inserts a fault (11) into the integrated circuit (10) with control and initialisation data words and monitors the effect of the fault on the functional logic (24). The fault control and initialisation data words are stored in timers (52, 54, 56), a fault word register (14), and an intermittent fault mode logic (60), and are decoded under the control of the controller (12) and a slaved timing and control generator (17) to load a fault type generator (16) which responds by supplying a fault type signal (FAULTn) to a fault insertion interface (18) which thereupon inserts the required fault into functional logic (24) by appropriate modification of the coupling between an output signal (N) from and and an input signal FSIGNAL(N) to the functional logic (24).

A Deterministic Approach to Adjacency Testing for Delay Faults

Abstract: Adjacency testing for delay faults is examined in both theory and implementation. We shall show that the necessary and sufficient conditions for adjacency testability yield an efficient method of robust delay test generation. Empirical results (including several different cost measurements) are presented which demonstrate that our technique: (1) achieves high fault coverages under both the robust and nonrobust delay fault models and (2) is cost effective.

Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits

Abstract: A methodology relating physical defects to the circuit-level faulty behavior caused by these defects and a fast algebraic implementation to provide a realistic fault list are proposed. In conjunction with the obtained statistical data on the likelihood of each fault and the knowledge of its best observable electrical manifestation, a solid basis for an effective and powerful test pattern generation is provided. To achieve an accurate modeling of bridging faults, a novel fault model, the large-scope short, is developed and implemented. In contrast to other fault analysis procedures which use time-consuming simulation methods to generate or induce physical defects, the proposed Fantestic methodology is very fast in extracting defects and converting them to a ranked fault list. The analysis of some sample CMOS circuits illustrates the effect of different physical defects on circuit-level faults. >

Smart power driver system for a motor vehicle

Abstract: An electrical power driver system with fault monitoring provision for both a self test mode and a normal operating mode. During the self test mode, the power driver is momentarily actuated during test intervals and its output compared to a predetermined value for providing self test fault indications. Each power driver is sampled and an indication provided of whether the fault is new or old in addition to providing a count of faults. During normal operation, monitoring circuitry provides indications of a plurality of fault types including over temperature, open circuit, short to ground, and short to voltage. A determination is made of whether each fault type is new or old and a count of faults provided. Output formatting provides indications of fault type, fault count, and whether the fault is intermittent or hard.

Detecting stuck-open faults with stuck-at test sets

Abstract: Simulations of CMOS combinational circuits have been conducted to determine the relationship between stuck-at and stuck-open fault coverage. The results suggest that node activity is more important to stuck-open fault coverage than test length by itself. Reordering test sets so that node activity is increased resulted in increased stuck-open fault coverage. It is important to note that the reordering of the test sets requires an analysis of fault-free simulations; no fault simulations need to be done. It has been shown that all but some minimum-length test sets can easily achieve the 75% stuck-open fault coverage required by the DoD (US Department of Defense), and pseudorandom tests, which have high measures of node activity, can be expected to have over 90% stuck-open fault coverage

Method of fault protection for a microcomputer system

Abstract: The present invention is a method of fault protection for a microcomputer system. The method determines whether the system returns to a normal or special operating mode if a fault is detected by determining the microprocessor's past history before the fault occurred thereby allowing the microprocessor to get back on track in an appropriate manner.

The Test Engineer's Assistant: a support environment for hardware design for testability

Abstract: A description is given of TEA (Test Engineer's Assistant), a CAD (computer-aided design) environment developed to provide the knowledge base and tools needed by a system designer for incorporating testability features into a design. TEA helps the designer meet the requirements of fault coverage and ambiguity group size. Fault coverage is defined as the percentage of faults that can be detected out of the population of all faults of a unit under test with a particular test set. An ambiguity group is defined as the smallest hardware entity in a given level of the system design hierarchy (that is, board, subsystem, and system) to which a fault can be isolated. The fault model considered throughout is the single stuck-at fault model. An example application of TEA is included. >

The testability of a modified Booth multiplier

Abstract: The author describes the generation of the test view of a multiplier-accumulator based on a modified Booth algorithm. It is shown that an algorithm can be found that rapidly generates the test patterns as a function of the parameters of the module. The fault model used is an extension of the traditional stuck-at model switch-level faults occurring in pass transistor logic. To achieve full testability, only slight modifications on the hardware of the multiplier-accumulator are necessary. It is possible to generate a set of test patterns that is independent of the size of the multiplier-accumulator. >

Logic performance verification and transition fault detection

Abstract: In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.

Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits

Abstract: In this paper we investigate two aspects regarding the detection of stuck-open (SOP) faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequence of stuck-at test sets. The performance of the proposed method is compared with that of a competing method. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage.

Application of window comparator to majority operation

Abstract: A fail-safe majority operation circuit capable of immediately reporting faults by utilizing multiple-valued signals is proposed, and the concrete configuration of the fail-safe majority operation circuit is clarified. The fail-safe majority operation circuit is defined as a circuit that has majority operation output signals and fault inspection output signals, never produces an output signal 1 in the event of any fault in its component devices when the operation output should be zero, and produces no wrong inspection output signals even if one input signal is erroneous. The fail-safe majority operation circuit is composed of fail-safe AND gates that have threshold values and are called window comparators. >