Showing papers on "Voltage-controlled oscillator published in 1998"

A fully integrated CMOS DCS-1800 frequency synthesizer

Abstract: A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 /spl mu/s, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset.

Frequency synthesizer systems and methods for three-point modulation with a DC response

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and to the divided signal, and thereby produce a first error signal. A sigma deltamodulator is responsive to a modulation input to produce the divided control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

On-channel transceiver architecture in a dual band mobile phone

Abstract: According to a second embodiment of the invention, a mobile phone receiver comprises a first down converter using a first local oscillator frequency which can be tuned in frequency steps by a programmable digital frequency synthesizer PLL which is locked to a reference frequency. The first down converter converts received signals to a first IF for filtering. A second down converter using a second local oscillator converts first IF signals to a second IF. The second local oscillator frequency is generated using a second digital frequency synthesizer PLL which locks the second oscillator to the reference frequency. A third down converter mixes the transmit frequency with the first local oscillator frequency to produce a lock frequency. A third digital frequency synthesizer PLL compares the lock frequency and the reference frequency to control generation of the transmit frequency.

Digital radiofrequency transceiver

Abstract: A method for radiofrequency (RF) transmission of digital information includes generating an RF signal using a voltage-controlled oscillator (VCO), stabilizing the RF signal from the VCO by providing an error signal from a phase-locked loop (PLL) to an input of the VCO, and combining the digital information with the error signal of the PLL input to the VCO, thereby causing variations in frequency of the RF signal from the VCO that represent the digital information. Apparatus for RF transmission of digital information includes a VCO, the VCO arranged to generate an RF signal, a PLL, the frequency input of the PLL coupled to the RF signal output of the VCO, an encoder, the encoder arranged to convert the digital information into a form where it has a data rate faster than a response time of the PLL, and a coupler, the coupler coupling both the error signal output of the PLL and the encoded digital information to an input of the VCO.

Method and apparatus for providing coarse and fine tuning control for synthesizing high-frequency signals for wireless communications

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a more general terms, a frequency synthesizer is disclosed having a first variable and a second capacitance circuits and frequency control circuitry to coarsely tune the output frequency by adjusting the first control signal and to finely tune the output frequency by adjusting the second control signal.

A fully integrated VCO at 2 GHz

Abstract: An integrated voltage-controlled oscillator (VCO) at a frequency of 2 GHz is implemented in a f/sub T/= 25 GHz standard bipolar process. The phase noise of the VCO is -136 dBc/Hz at 4.7 MHz frequency offset. The LC-resonator uses vertically coupled on-chip inductors and integrated tuning diodes. Due to the poor performance of integrated resonators on silicon ICs, oscillators with phase noise meeting requirements of wireless applications are difficult to integrate. With fully integrated designs only the standards for cordless phones, for instance DECT, can be achieved. The critical point in the DECT-specification is the emission of the transmitter due to intermodulation in the third adjacent channel, that must be <-47 dBm. This value is measured with an integration bandwidth of 1 MHz centered at the nominal center frequency. With a channel-spacing of 1.728 MHz the third adjacent channel is located 5.184 MHz from the actual transmit channel frequency. The beginning of the integration bandwidth is at an offset frequency of 4.684 MHz related to the nominal frequency of the transmit channel. This is the offset frequency, at which the specification must be met. The resulting noise requirement is -132 dBc/Hz at a offset frequency of 4.684 MHz, when the integration bandwidth and the transmit output power of 25 dBm are taken into account.

Method and device relating to supervision and control of an oscillator signal

Abstract: The present invention relates to methods and devices for such control and supervision of an oscillator signal from a controllable oscillator that is done mainly to control the frequency variation of the oscillator signal. According to the invention, the controllable oscillator is controlled by a controlling voltage, which in turn is modified by a correction signal, generated in a control loop. A time discrete representation of a secondary phase is generated in the control loop, the secondary phase corresponding to a frequency being the difference between the frequency of the oscillator signal and a constant frequency. A time discrete approximation signal is generated in dependence of the time discrete representation of the secondary phase. A time discrete error signal is generated in dependence of the time discrete approximation signal, the time discrete error signal indicating the difference between the actual frequency slope of the oscillator signal and a desired frequency slope. The correction signal is generated in dependence of the time discrete error signal. The control loop can also be adaptive, meaning that data from one control sequence is being used in a later control sequence.

A 3.5 mW 2.5 GHz diversity receiver and a 1.2 mW 3.6 GHz VCO in silicon-on-anything

Abstract: In this paper, first results of radio-frequency (RF) circuits processed in a novel silicon bipolar technology called silicon on anything (SOA) are presented. This technology was developed with the application of low-power, high-frequency circuits in mind. Three test ICs are discussed: a fully integrated 3.6-GHz voltage-controlled oscillator, a fully integrated 2.5-GHz diversity receiver front end, and an intermediate-frequency IC containing channel selectivity and demodulation circuits. Measurement results show that using this technology, significant power savings are possible for RF circuits.

An agile ISM band frequency synthesizer with built-in GMSK data modulation

Abstract: In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range.

Phase locked loop control via inner and outer feedback control circuits

Abstract: A phase locked loop includes at least one control circuit, where a voltage-controlled oscillator provides an output frequency which is arranged to strive to follow an input frequency. The phase locked loop also includes an outer, slow, negative feedback control circuit, having the input frequency as a setpoint, the output frequency as a process value and an outer output signal. The phase locked loop also includes an inner, fast, negative feedback control circuit, having the sum of a reference frequency from a stable oscillator and the outer output signal as a setpoint, the output frequency as the process value and an inner output signal for controlling the voltage controlled oscillator.

Radio transceiver on a chip

Abstract: An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

Dual band transmitter for a cellular phone comprising a pll

Abstract: Disclosed is a dual band wireless phone, such as a cellular phone for a mobile communications system, with a dual band transmitter that includes a phase-locked loop (PLL). The dual band transmitter includes first and second power amplifiers and the PLL. The first power amplifier has a first input for a first signal at a first radio frequency band, and a first output for an amplified first signal. The second power amplifier has a second input for a second signal at a second radio frequency band and a second output for an amplified second signal. The outputs of the power amplifiers are connectable to an antenna. The PLL generates two output frequency ranges and includes a voltage-controlled oscillator (VCO) which has a first output connected to the first power amplifier and generates a first signal. A frequency multiplier has an input connected to the first output of the VCO and a second output connected to the second power amplifier. The frequency multiplier receives the first signal and generates the second signal.

Voltage controlled oscillator (VCO) frequency gain compensation circuit

Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V control . Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V control . Accordingly, the magnitude of total control current is dominated by the transistor-provided component, and assumes a square relationship, with respect to the input control voltage. This square-law current-voltage gain characteristic compensates for the inversely mirrored frequency gain characteristic of the ring oscillator in order to attain a reduced frequency gain variation for the overall VCO, with respect to control voltage variations. This reduction in variation translates to a reduced variation in the frequency gain of the VCO with respect to temperature variations when the VCO is used in a phase locked loop (PLL) circuit.

Self-calibrating phase-lock loop with auto-trim operations for selecting an appropriate oscillator operating curve

Abstract: A phase-lock loop (PLL) has an oscillator having a plurality of operating curves. During PLL auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal PLL operations. In particular embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO. During the PLL auto-trim operations, a state machine applies a sequence of digital control input values to the VCO to select different VCO operating curves until an appropriate operating curve for the present PLL application is found. In different embodiments, the state machine uses different signals to determine whether the center frequency of each operating curve in the sequence is above or below the desired nominal operating frequency for the VCO, and select one such operating curve for use in normal operations.

Frequency jittering control for varying the switching frequency of a power supply

Abstract: EMI emission is reduced by jittering the switching frequency of a switched mode power supply. An oscillator with a control input for varying the oscillator's switching frequency generates a jittered clock signal. In one embodiment, the oscillator is connected to a counter clocked by the oscillator. The counter drives a digital to analog converter, whose output is connected to the control input of the oscillator for varying the oscillation frequency. In another embodiment, the oscillator is connected to a low frequency oscillator whose low frequency output is used to supplement the output of the oscillator for jittering the switching frequency. The invention thus deviates or jitters the switching frequency of the switched mode power supply oscillator within a narrow range to reduce EMI noise by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment.

A wide-band tuning system for fully integrated satellite receivers

Abstract: The building blocks for a low-power tuning system that reduces the phase noise of integrated VCO's are described. The multimodulus prescaler, the phase frequency detector, and the wide-band charge pump have been integrated in a standard bipolar technology with 9-GHz n-p-n transistors and 200-MHz p-n-p transistors. The maximum input frequency of the multimodulus prescaler is 3.2 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz, and the 3-dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables the use of fully integrated VCO's with relatively high phase noise for reception of satellite digital signals.

A practical quality factor tuning scheme for IF and high-Q continuous-time filters

Abstract: An important aspect of reducing power and area of RF/IF systems is putting high-frequency filters on-chip instead of using off-chip crystal, ceramic, or SAW filters now used. The largest challenge facing designers is the vulnerability of high-frequency and high-Q continuous-time filters to parasitics and process variations, requiring automatic tuning of both center frequency and quality factor. Automatic center frequency tuning is well documented, with accuracies of <1% error. Q-tuning is not as well defined, with the best reported results at about 20-30% error. The Q-tuning method proposed here improves the accuracy of Q-tuning, with experimental Q-tuning error about 1%. The basis for the proposed method is the magnitude-locked-loop (MLL) Q-tuning technique. The scheme removes the peak detectors and utilizes the continuous-time adaptive LMS algorithm to update the biquad quality factor. As a test verification of the proposed Q-tuning scheme, a fourth order OTA-C 10.7 MHz bandpass filter is designed and fabricated in a 1.2 /spl mu/m n-well CMOS process. The filter consists of two cascaded biquads, each with a desired quality factor of 20 and the same center frequency. Center frequency tuning is provided by the conventional phase-locked loop using a voltage controlled oscillator scheme, and Q-tuning is by the proposed scheme. The reference signal for the Q-tuning circuit is simply the frequency control oscillator's output.

Method and apparatus for measuring localized voltages on programmable integrated circuits

Abstract: A method is described for measuring localized operating temperatures and voltages on an integrated circuit. The integrated circuit includes an oscillator circuit with a frequency that varies with temperature and/or applied voltage. The frequency of the oscillator is then determined, using a constant voltage, for a number of temperatures to establish a known relationship between oscillation frequency and temperature. Once the relationship is known, a similar oscillator is included within or adjacent a second circuit of the integrated circuit. The operating temperature or operating voltage of the second circuit may then be determined by monitoring the frequency of the oscillator while the second circuit is operational.

Digital frequency synthesis by sequential fraction approximations

Abstract: A fractional synthesis approach and arrangement are presented which achieve fine frequency resolution with low phase noise while at the same time retaining a high phase comparison frequency/fast frequency changing speed. An output signal having a desired output frequency is generated by a voltage controlled oscillator (VCO). An output divider divides the output frequency by an output divisor N to produce an output pulse train. The output divisor N may be equal to an output integer N or the output integer plus one N+1, for example, and may change during the generation of a single output frequency. For different desired output frequencies, the value of the output integer N may be varied. A reference divider divides a reference frequency by a reference divisor M to produce a reference pulse train. The reference divisor M may be equal to a reference integer M or the reference integer plus one M+1, for example, and may change during the generation of a single output frequency. A fractional controller may vary the value of the divisor M between successive pulses from the reference divider to produce a mean output pulse frequency having a non-integral relationship to the reference frequency. A phase error detector compares the pulse trains and generates a phase error signal. This signal, which may be filtered or otherwise processed, controls the VCO to produce the output signal at the desired output frequency.

Phase interpolated fractional-N frequency synthesizer with on-chip tuning

Abstract: A phase interpolated frequency synthesizer with on chip tuning includes a voltage controlled oscillator, a fractional-N divider, phase compensation and on chip tuning circuits, a phase detector, and a loop filter. The phase compensation and on chip tuning circuits compensate for the phase lag from the fractional-N divider. The phase compensation circuit can include a series of voltage controlled delay elements with the tuning circuit providing a control voltage.

A fully integrated 2.7 V 0.35 /spl mu/m CMOS VCO for 5 GHz wireless applications

Abstract: The wireless market drives the integration of RF circuits on common digital CMOS technologies. Full integration of the tank circuit, low-phase noise and high current efficiency are desirable for voltage-controlled oscillator (VCO) circuits. The design of fully-integrated non-relaxation VCOs in modern digital technologies is limited by the lack of high-quality passive components. For example, the quality of on-chip inductors is severely limited due to ohmic losses, especially in common CMOS technologies with low-resistivity substrates. Using transistor parasitics as tank capacitors, large active devices can be used in the VCO so current efficiency is optimized while phase-noise performance and a high center frequency are maintained. For a 0.7-2.7 V tune voltage range, a 200 MHz or 4.3% tuning range is available. This VCO can be used for 5 GHz wireless applications with a typical IF frequency of several hundred MHz.

Apparatus for low power radio communications

Abstract: A low-power radio transceiver comprising a loop filter/sample and hold circuit (66) for storing the VCO (32), control voltage (40), thereby allowing the PLL in the synthesizer (2), to be opened and closed with minimum output frequency drift. Power consumption is reduced by partially powering down the synthesizer (2) during open-loop operation. Automatic frequency control is provided in the receiver.

A highly linear frequency ramp generator based on a fractional divider phase-locked-loop

Abstract: A highly linear analog frequency ramp generator based on a fractional divider concept is presented. The frequency ramp linearity achievable in this fractional phase-locked-loop configuration is better than 10/sup -4/. This value is revealed by numerical simulations as well as by measurements performed. With a prototype synthesizer implemented in a FMCW-radar system suitable for distance and velocity measurements.

Systems and methods for automatic deviation setting and control in radio transmitters

Abstract: A frequency modulation (FM) radio transmitter, such as a cellular telephone, includes an automatic deviation control system to automatically compensate for varying sensitivity of the FM transmitter. The FM transmitter includes a phase lock loop including a controlled oscillator that produces a frequency modulated input signal on an output channel frequency in response to a control input that is applied thereto. A scaler is responsive to the input signal and to at least one scaling content, to scale the input signal based upon the at least one scaling constant and to provide the scaled input signal to the phase lock loop to produce the frequency modulated input signal on the channel frequency. An automatic deviation control system measures the control signal that is applied to the controlled oscillator when tuned to one of the plurality of output channel frequencies and updates at least one of the scaling constants based upon the measured control input, to thereby provide automatic deviation control.

A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances

Abstract: A 1.4-GHz LC voltage-controlled oscillator has been implemented in a MOSIS 0.5-/spl mu/m CMOS process. Complementary cross-coupled PMOS and NMOS transistors enhance single-ended symmetry at each of the resonant nodes, reducing close-in phase noise. Tapped bond wires provide a resonant tank with high Q. At an offset frequency of 100 kHz, the measured phase noise is -10/sup 7/ dBc/Hz with 3 mW power dissipation from a 3.0 V supply. NMOS gate capacitors achieve a 17% tuning range.

A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances

Abstract: A 1.4-GHz LC voltage-controlled oscillator has been implemented in a MOSIS 0.5-/spl mu/m CMOS process. Complementary cross-coupled PMOS and NMOS transistors enhance single-ended symmetry at each of the resonant nodes, reducing close-in phase noise. Tapped bond wires provide a resonant tank with high Q. At an offset frequency of 100 kHz, the measured phase noise is -10/sup 7/ dBc/Hz with 3 mW power dissipation from a 3.0 V supply. NMOS gate capacitors achieve a 17% tuning range.

Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a digital control signal is disclosed to control the overall capacitance for the discretely variable capacitance circuit, and a variable control signal is disclosed to control an overall capacitance for the continuously variable capacitance circuit. In addition, the output frequency may be varied by adjusting either the digital control word or the variable control word.

Properties of an oscillator slaved to a periodically interrogated atomic resonator

Abstract: In advanced atomic resonators, such as those using a fountain of cold cesium atoms or an ensemble of stored ions, the atomic medium is interrogated periodically, and the control signal of the slaved oscillator is updated at equally spaced time intervals. We analyze the properties of the output frequency of these frequency standards. We establish the equations that describe the time behavior of this frequency. We give the stability condition and the transient response of the frequency feedback loop, the response to systematic frequency changes of the free running oscillator, the frequency stability for given free-running oscillator noise and given optical detection noise, and the limitation of the frequency stability by down-conversion of the intrinsic oscillator frequency noise (Dick effect). We point out that a second integration in the feedback loop may not improve significantly the rejection of slow perturbations, unless a condition relative to the timing of the atom-field interaction is verified.

High performance inter-chip signalling

Abstract: The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the performance of digital systems In intra-system interfaces where both latency and bandwidth are important, source-synchronous parallel channels have been adopted as the most effective solution This work investigates receiver and clocking circuit design techniques for increasing the signalling rate and robustness of such channels One of the main problems arising in the reception of high speed signals is the adverse effects of high frequency noise To alleviate these effects, a new class of receiver structures that utilize current integration is proposed The integration of current on a capacitor based on the incoming signal polarity effectively averages the signal over its valid time period, therefore filtering out high frequency noise An experimental transceiver prototype utilizing current integrating receivers was designed and fabricated in a 08 $\mu$m CMOS technology The prototype achieves a signaling rate of 740 Mbps/pin operating from a 33-V supply with a bit error rate of less than 10$\sp{-14}$ The second major challenge of inter-chip communication is the design of clock generation and synchronization circuits Delay locked loops are an attractive alternative to VCO-based phase locked loops due to their simpler design, intrinsic stability, and absence of phase error accumulation One of their main problems however is their limited phase capture range A dual loop architecture that eliminates this problem is proposed This architecture employs a core loop to generate finely spaced clock edges, which are then used by a peripheral loop to generate the output clock through phase interpolation Due to its digital control, the dual loop can offer great flexibility in the implementation of phase acquisition algorithms A dual DLL prototype was fabricated in a 08 $\mu$m CMOS technology The prototype achieves 80KHz-400MHz operating range, 12-ps rms jitter and 04-ps/mV jitter supply sensitivity

Phase locked loop using a schmitt trigger block

Abstract: A phase locked loop (PLL) circuit is described which uses a Schmitt trigger block (28) to achieve a very small steady state phase error at an input of a phase comparator block (21) over the entire PLL lock voltage range. The amount of hysteresis which each Schmitt trigger circuit (281, 282) in the Schmitt trigger block (28) has depends on the damping factor ζ of the PLL circuit as well as the temperature and voltage coefficients of a VCO's input voltage. The midpoint of the positive and the negative thresholds of the hysteresis curve of each Schmitt trigger circuit (281, 282) is set by the current voltage characteristics of charge pump circuits in a charge pump block (22). Responsive to the PLL's lock voltage (VCNT), the Schmitt trigger block (28) commands a control logic circuit (29) to turn ON or turn OFF as the case may be PMOS pump UP transistors to that of NMOS pump DOWN transistors. It is this ratio which determines the PLL's steady state phase error. In one embodiment, a frequency divider (25) is used between the VCO (24) and the phase comparator block (21). In another embodiment, this divider (25) is removed and the output of the VCO is fed directly back to the phase comparator block.