Showing papers on "Wafer published in 1981"

Chemical Etching Characteristics of ( 001 ) InP

Abstract: The chemical etching characteristics of are studied through an mask in the solutions of various etching systems: (i) , (ii) , (iii) , (iv) , and (v) . The etched depth is evaluated by using a calibrated optical microscope. The etching profiles are examined by cleaving the wafer in orthogonal directions along the (110) and (10) planes. Various etching profiles, such as V‐shaped, reverse mesashaped ones, and nearly vertical walls, are formed by stripes being etched on the (001) planes. The indexes of the etch‐revealed planes are identified by making a comparison with the calculated angle between the (001) surface and etch‐side plane. The utility of these etching solutions is also discussed for a variety of device applications.

Phase transformation on and charged particle emission from a silicon crystal surface, induced by picosecond laser pulses

Abstract: Ultrafast melting and resolidification on a (111) sufarce of a silicon crystal wafer, induced by 20‐ps pulses at 532‐nm wavelength, is accompanied by the emission of charged particles. This emission is studied as a function of pulse energy, in combination with time‐resolved reflectivity changes and post‐annealing morphology. The data provide evidence that thermalization time for a dense carrier plasma and the lattice is shorter than 10−11 s.

Method for fabricating via holes in a semiconductor wafer

Abstract: A circuit pattern is formed on a front side surface of a semiconductor wafer and an apertured photoresist pattern is formed over the circuit pattern. Via holes are then formed by laser irradiating the wafer at sites corresponding to the photoresist apertures. The back side surface of the wafer is next metallized and this surface is adhered to a plating block by means of an adhesive layer. Electrical connection between the substrate and plating block is then made, the via holes are electroplated, and the substrate is separated from the plating block and adhesive layer.

Universal interconnection substrate

Abstract: A wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.

Ultra-thin microelectronic pressure sensors

Abstract: A plurality of thin pressure sensors are made by processing a first large wafer (20, 110) to provide a plurality of electronic devices (28, 122, 124, 125) having a characteristic which varies inversely with strain, and processing a second wafer (40) to provide a plurality of cavities (46) each registered on the second wafer so as to be registerable with a corresponding device on the first wafer. The wafers (20, 40, 110) have thick undoped silicon substrates (21, 41, 114) which are utilized as handles or carriers during the processing, and are stripped off by etching to a highly doped boron etch stop layer (22, 42, 112) when the processing has proceeded to a point where the need therefore has been satisfied. The first wafers (20, 110) are provided with a suitable pattern of borosilicate glass (except in the region where the pressure sensors are formed) so that the two wafers may be joined by a field assisted bonding at a suitable temperature in a vacuum. Electric contact to the devices is provided by holes (51, FIG. 9; 56-59 , FIG. 13) through the entire wafer.

On the diamond-cubic to hexagonal phase transformation in silicon

Abstract: An analysis of electron diffraction data from silicon wafers implanted with 80 keV As+ at high dose rates has shown the presence of a hexagonal phase of Si (a one-element wurtzite structure). The hexagonal silicon consists of small rod-like particles with an orientation relationship to the diamond-cubic (d.c.) silicon lattice given approximately by 〈0001〉hex | 〈110〉d.c. and 〈0110〉hex | 〈001〉d.c.. This hexagonal silicon may also be produced by indenting the wafer surfaces at about 500 to 600°C (Eremenko and Nikitenko 1972) which produces large platelets with {115}d.c. habit planes. A phase transformation scheme is proposed for the silicon dc to hexagonal transformation. It is argued that the transformation may be induced by a uniaxial compressive stress and therefore represents a stress-relief mechanism. A structure model of the dc-hexagonal interface is proposed which consists of five- to seven-membered atomic rings without dangling bonds.

Temperature control for wafer polishing

Abstract: A wafer workpiece polishing temperature control method and apparatus are provided wherein wafers are mounted upon a rotatable pressure plate assembly positioned in rotatable contact with a turntable assembly supported polishing pad, the turntable assembly having internal fluid cooling means, the wafer polishing temperature control being achieved through responsive closed loop electromechanical means activated by variation of polishing pressure upon the wafers and the polishing pad.

Technique for inspecting semiconductor wafers for particulate contamination

Abstract: A laser beam (88) is raster scanned over the surface of a patterned semiconductor wafer (66) at an angle normal thereto. A plurality of detectors, radially spaced from the wafer (66) and substantially coplanar therewith detect light scattered from contaminating particulate thereon. The detected light is converted into a video signal that is forwarded to a video monitor (84) to display the particulate material while eliminating the patterned surface background.

ZnO/SiO2-diaphragm composite resonator on a silicon wafer

Abstract: We report on a thickness-extensional-mode piezoelectric resonator consisting of a ZnO/SiO2 diaphragm supported by a silicon wafer. It is found that the temperature coefficient of frequency can be reduced to zero by adjusting the ZnO/SiO2 thickness ratio. A temperature coefficient of frequency as low as 10 ppm/°C was experimentally obtained.

Automatic wafer alignment technique

Abstract: This automatic wafer alignment technique may be used in a step-and-repeat photomicrolithographic exposure system accurately to prealign a wafer before exposure to the B-level and subsequent reticles, and automatically to align the wafer at each die site prior to exposure. A search technique optimizes location of the global targets used for wafer prealignment. The search begins at the most likely target position and proceeds through a search area established by the maximum expected rough prealignment error. A wafer alignment target configuration consisting of a cross with one elongated arm and a short crossbar is used to optimize target verification. To locate targets a video image is digitized and the average intensity at each video scan line and column is obtained and stored. This data is used to determine the presence in the video image of feature edges. A table of all such edges is established. These listed edges are correlated to determine all pairs of edges that may represent potential targets. From these, the best target is selected by comparing certain weighted parameters of each potential target.

Apparatus and method for plasma-assisted etching of wafers

Abstract: In a plasma-assisted etching apparatus and method designed to pattern silicon dioxide in a plasma derived from a mixture of trifluoromethane and ammonia, surfaces in the reaction chamber are coated with a layer of silicon. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Faceted low absorptance solar cell

Abstract: A solar cell includes a semiconductor wafer of one conductivity type with a front radiation receiving surface having a plurality of pyramidal apertures therein. The spacing of adjacent apertures is selected to maximize the escape of undesired radiation. A material with a high index of refraction fills the apertures and further enhances radiation escape. The surfaces of the wafer are provided with thin regions of opposite conductivity type. Two sets of electrodes are provided at selected locations on the rear side of the wafer. One set of electrodes contacts the region of opposite conductivity type on the rear side. The other set of electrodes contacts the wafer through openings in the region of opposite conductivity type.

Forming electrical interconnections through semiconductor wafers

Abstract: An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Soft X-ray imaging with a normal incidence mirror

Abstract: By sputtering, it is possible to make multilayered structures (layered synthetic microstructures or LSMs) with individual layers as thin as a fraction of a nanometer. These techniques have been used to make a multilayered interference mirror to reflect carbon K X rays (at a wavelength of 4.48 nm) at normal incidence. The structure consists of 76 layers of tungsten of thickness 0.765 nm with layers of carbon (thickness 1.510 nm) interspersed, deposited on a 111 line type silicon wafer substrate. This LSM was formed into a concave mirror of radius approximately 1.1 m by bending the substrate, and used in an optical set-up to form images of grids illuminated by an X-ray source. The mirror was found to have a resolution of 5 lines/mm and an efficiency, integrated over the CK band, of between 4 and 8%.

Gold gettering in silicon by phosphorous diffusion and argon implantation: Mechanisms and limitations

Abstract: The ability of phosphorus diffusion or argon implantation to remove gold from a silicon wafer has been studied. Both the gettering layer and the gettered substrate have been analyzed for their gold content by complementary techniques such as Rutherford backscattering, neutron activation analysis, and deep level transient spectroscopy. Phosphorus diffusion allows a very efficient gold removal when surface concentration CS and temperature T are kept in a well‐defined domain (high CS , low T). On the contrary, the gettering is ineffective in the low CS , high T domain. The boundary between these two domains is found to be an iso‐Fermi level curve corresponding to Ec −EF = 0.15 eV. These results are explained by the formation of a negatively charged (P, Au) pair. Argon implantation induces a damaged layer which is found to accomodate large amounts of metal. However, at annealing temperatures higher than 800 °C, gold is found to remain in the bulk at noticeable concentrations which increase with temperature. S...

Cobalt silicide metallization for semiconductor integrated circuits

Abstract: In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400° C. to 500° C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C02 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700° C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi2). Subsequently, deposition of an in situ doped layer (33) of polycrystalline silicon (polysilicon) on the cobalt disilicide contacting the monocrystalline silicon portions--followed by gettering, deposition of a layer (34) of aluminum, and standard etch-patterning of the aluminum and polysilicon layers--completes the metallization of the desired MOSFET structures on the silicon wafer.

Heat-pulse annealing of arsenic-implanted silicon with a CW arc lamp

Abstract: A new annealing method is introduced whereby a silicon wafer is irradiated by a short heat pulse generated by CW lamps. Results of the annealing process obtained from medium-dose arsenic-implanted silicon are similar to those obtained from nonmelting short heat treatments-complete activation of the implanted dopant with no diffusion or distortion of the impurity profile. Investigation of the crystal structure by means of TEM indicates a lack of any defects down to a resolution of 10 A. Because of its simplicity, heat-pulse annealing has the potential of higher throughput in comparison to equivalent laser or electron-beam irradiation.

Mos type semiconductor device

Abstract: PURPOSE:To eliminate the insulating breakdown of an insulating oxidized film layer due to high frequency surge by increasing the thickness of the film layer of an input unit larger than the other part in response to the peak value of the surge. CONSTITUTION:An Si3N4 11 is grown on the overall surface of a P type silicon wafer 1, an Si3N4 of a region 10 is removed, a window is opened (a), and a silicon oxidize layer 2a is formed on the opened region 10 (b). Then, a silicon oxide layer 2b and further a silicon oxide layer 2c are formed based on similar LOCOS method (a silicon local oxidizing method) (c) and (d). Thereafter, polycrystalline silicons 5, 5a are formed on silicon oxide layers 2a, 2c (e), and then or simultaneously a gate 8 is formed by diffusion (f). Metal wirings 3, 5 are eventually formed by the deposition of aluminum (g).

Regrowing selectively formed ion amorphosized regions by thermal gradient

Abstract: Processes for forming a wafer having SOS structure are provided. A single crystal silicon layer is formed on a principal plane of a sapphire substrate. An amorphous portion is formed in a silicon layer leaving its surface portion of predetermined depth as it is and by injecting Si + into the single crystal silicon layer. This amorphous portion reaches the interface of sapphire substrate. A wafer thus formed is placed on a cooling table in a furnace. The substrate is fixedly bonded onto the cooling table with indium and cooled to a predetermined temperature. A temperature higher than that applied to the sapphire substrate is applied to the silicon layer including the amorphous portion using a heater arranged in the furnace and N 2 gas flowing into the furnace. The SOS wafer is then returned to room temperature.

Activation of arsenic‐implanted silicon using an incoherent light source

Abstract: We report that continuous, incoherent light from a xenon arc lamp can be used to completely activate implanted Si (100) samples (75As+:100 keV, 1×1015 cm−2) with negligible dopant redistribution and excellent uniformity (sheet resistivity variation less than ±2% over a 3‐in.‐diam wafer). An entire 3‐in. wafer could be activated in only about 10 sec without relative motion of wafer and light beam. The extent to which implant damage was removed by the incoherent light anneal is qualitatively indicated by the carrier mobilities which were within 10% of single‐crystal values.

Laser photodeposition of refractory metals

Abstract: We report the deposition of the refractory metals chromium, molybdenum, and tungsten through the laser‐induced gas‐phase photolysis of their respective hexacarbonyls A copper, hollow cathode laser was used at ultraviolet wavelengths matched to peaks in the absorption spectra of the carbonyl molecules Localized room‐temperature metal deposition was achieved by focusing the beam into a cell containing the carbonyl gas and helium as a buffer No major differences were noted for deposition on a polished silicon wafer, a thermally oxidized silicon wafer, and a quartz flat

Method of dicing a semiconductor wafer

Abstract: A method of dicing a semiconductor wafer in which a physical discontinuity is formed on the surface of the wafer on both sides of a dicing line to limit the spreading of cracks and chips generated during dicing. Thereafter, the semiconductor wafer is diced to separate the pellets.

Radiation Annealing of GaAs Implanted with Si

Abstract: The use of radiation from halogen lamps to anneal implanted GaAs has been studied. Semi-insulating GaAs wafers implanted with 3×1012 cm-2 silicon at 70 keV were completely activated by 5 seconds rediation with or without encapsulation. The wafer temperature reached 950°C. This annealing method minimizes the thermal conversion of semi-insulating GaAs wafers.

Growth of extremely uniform layers by rotating substrate holder with molecular beam epitaxy for applications to electro-optic and microwave devices

Abstract: Integrated optics and integrated microwave circuits require extremely uniform epitaxial layer thicknesses, composition profiles, and doping profiles. With a sample rotating mechanism, molecular beam epitaxy can for the first time prepare GaAs and AlxGa1−xAs layers with thickness variation of less than 1% over a lateral dimension of 5 cm. The variation of AlAs mole fraction of the Al0.3Ga0.7As over a 10‐cm2 area was less than 0.4%. The variation of the ’’pinch‐off’’ voltage for a field effect transistor structure was less than 1.4% over a 10‐cm2 wafer. These results represent the most uniform epitaxial layers ever prepared with any crystal growth technology.

Apparatus for automatic lapping control

Abstract: Apparatus for automatic lapping control, based on imbedding an electrode in a lap plate of a lap machine and including at least one piezoelectric wafer in the lap load. Connected with the electrode is an automatic control circuit used for sensing the resonance frequency of the piezoelectric wafer and for terminating lapping when the resonance frequency reaches a presetable target frequency. Also connected with the electrode is an impedance comparator circuit used for sensing the presence and absence of a piezoelectric wafer at the electrode face and for activating the automatic control circuit in the presence of a wafer and deactivating the control circuit in the absence of a wafer.

Automatic wafer orienting apparatus

Abstract: An automatic wafer orienting apparatus comprising a first orienting device for driving and rotating a wafer thereby orienting the wafer while utilizing a peripheral edge and an orientation cut thereof as the guide, a device for disengaging the thus oriented wafer from the first wafer orienting device, and a second wafer orienting device for re-orienting the wafer by pressing a lateral edge and an orientation cut thereof against orienting members provided on a wafer chuck.

Cathode for etching

Abstract: A cathode for reactive ion etching is provided which improves the etch rate and the uniformity of etching on the object etched. The cathode has a quartz plate with a series of recesses having disks therein of the same material as the object to be etched and a ring of that same material around the outer edge of the plate. In a preferred embodiment a cathode for etching silicon wafers has silicon disks recessed in a quartz plate at each wafer holding position and a ring of silicon around the outer edge of the plate.

FET fabrication using maskless ion implantation

Abstract: Focused ion beams from Au–Si, Au–Be, and B–Pt liquid–metal–alloy ion sources have been used to implant GaAs and Si. An Al stopping layer on the wafers was used to trap the Au and Pt ions. Hall mobilities consistent with those in bulk materials have been obtained for B‐doped Si and Be‐doped GaAs. In addition, a 2000‐A‐diam Au–Si focused ion beam was used to implant the doped regions of GaAs metal‐semiconductor gate field‐effect transistors. The 140‐keV Si++ beam component was deflected under computer control to implant 8×50 μm active channel regions and 16×50 μm contact regions. The devices were metalized using conventional lithography. DC electrical characteristics of the 1.5‐μm‐gate‐length devices are comparable to those of conventionally processed devices of identical geometry.

High-Rate Reactive Ion Etching of SiO 2 Using a Magnetron Discharge

Abstract: A magnetron discharge has been used for high-rate reactive ion etching. A SiO2 wafer situated on the cathode was etched by scanning a rectangular permanent magnet under the cathode coupled with a power of 13.56 MHz which generated an intense plasma loop over the cathode. The SiO2 etch rate of 1.1 µm/min and the SiO2/Si selective ratio of 9.5 was achieved by employing CHF3 under a magnetic field of 1 k Gauss and an input rf power of 1.6 W/cm2. This condition lowers the ion bombarding voltage of 80 A on the Si surface. The plasma scanning and an electrostatic chacking of the wafer to the wafer-cooled cathode produces an anisotropic etched feature without photoresist degradation.

Growth of high-purity semi-insulating bulk GaAs for integrated-circuit applications

Abstract: Growth of high-purity bulk semi-insulating GaAs by the Liquid-Encapsulated Czochralski (LEC) method has produced thermally stable, high-resistivity crystals suitable for use in direct ion implantation. Large round substrates have become available for integrated-circuit processing. The implanted wafers have excellent electrical uniformity (±4 percent V p ) and have shown electron mobility as high as 4800cm2/V.s for Se implants with 1.7 × 1017cm-3peak doping. Careful control of background doping through in situ synthesis has produced GaAs with Si concentrations as low as 6 × 1014cm-3grown from SiO 2 crucibles. Detailed results of qualification tests for ion implantation in LEC GaAs will be discussed. Feasibility of successful high-speed GaAs large-scale integrated circuits using LEC substrates will be described.