A. Upham

TL;DR: In this paper, the authors present a new ETSOI CMOS integration scheme that incorporates all benefits from their previous unipolar work, and demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at I off = 300 pA/m, V DD = 0.9V, and L G = 25nm.

TL;DR: A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths and modulates device Vt, thus providing an additional knob to enable multi-Vt while maintaining undoped channels for all devices.

TL;DR: It is demonstrated in 20nm ground rules that Vt is able to tune by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.

TL;DR: In this paper, a gate length of 25nm and competitive drive currents of 1.27 mV·µm were achieved by using a gate-first high-k/metal and raised source/drains (RSD).

TL;DR: In this article, a zero-silicon loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling structural demonstration of sub-2 nm ETSOI.