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Balasubramanian S. Pranatharthi Haran
Researcher at IBM
Publications - 46
Citations - 1084
Balasubramanian S. Pranatharthi Haran is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Trench. The author has an hindex of 16, co-authored 46 publications receiving 854 citations.
Papers
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Proceedings ArticleDOI
FinFET performance advantage at 22nm: An AC perspective
Michael A. Guillorn,Josephine B. Chang,A. Bryant,Nicholas C. M. Fuller,Omer H. Dokumaci,X. Wang,J. Newbury,Katherina Babich,John A. Ott,Balasubramanian S. Pranatharthi Haran,R.R. Yu,Christian Lavoie,D. Klaus,Y. Zhang,E. Sikorski,W. Graham,B. To,Michael F. Lofaro,James A. Tornello,Dinesh Koli,Bin Yang,A. Pyzyna,D. Neumeyer,Marwan H. Khater,Atsushi Yagishita,H. Kawasaki,Wilfried Haensch +26 more
TL;DR: In this article, the authors estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs.
Proceedings ArticleDOI
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Ruilong Xie,Pietro Montanini,Kerem Akarvardar,Neeraj Tripathi,Balasubramanian S. Pranatharthi Haran,Scott C. Johnson,Terence B. Hook,Bassem Hamieh,D. Corliss,Junli Wang,Xin Miao,John R. Sporre,Jody A. Fronheiser,Nicolas Loubet,Min Gyu Sung,Stuart A. Sieg,Shogo Mochizuki,Christopher Prindle,Soon-Cheon Seo,Andrew M. Greene,Jeffrey C. Shearer,Andre Labonte,Su Chen Fan,Lars W. Liebmann,Robin Chao,Abraham Arceo,Kisup Chung,K. Cheon,Praneet Adusumilli,H. P. Amanapu,Zhenxing Bi,Jungho Cha,H. Chen,Richard A. Conti,Rohit Galatage,Oleg Gluschenkov,Vimal Kamineni,Ki-chul Kim,Lee Choonghyun,F. Lie,Zuoguang Liu,Sanjay Mehta,Eric R. Miller,Hiroaki Niimi,Chengyu Niu,Chanro Park,D. Park,Mark Raymond,Bhagawan Sahu,Muthumanickam Sankarapandian,Shariq Siddiqui,Richard G. Southwick,Lei Sun,Charan V. V. S. Surisetty,Stan D. Tsai,S. Whang,Peng Xu,Y. Xu,C.-C. Yeh,Peter Zeitzoff,J. Zhang,James Chingwei Li,James J. Demarest,John C. Arnold,Donald F. Canaperi,Derren N. Dunn,Nelson Felix,Dinesh Gupta,Hemanth Jagannathan,S. Kanakasabapathy,Walter Kleemeier,C. Labelle,M. Mottura,P. Oldiges,Spyridon Skordas,Theodorus E. Standaert,Tenko Yamashita,Matthew E. Colburn,Myung-Hee Na,Vamsi Paruchuri,S. Lian,R. Divakaruni,T. Gow,Seng Luan Lee,Andreas Knorr,Huiming Bu,Mukesh Khare +86 more
TL;DR: In this paper, the authors present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology.
Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Proceedings ArticleDOI
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
Qing Liu,M. Vinet,J. Gimbert,Nicolas Loubet,Romain Wacquez,L. Grenouillet,Y. Le Tiec,Ali Khakifirooz,Toshiharu Nagumo,Kangguo Cheng,H. Kothari,Chanemougame Daniel,F. Chafik,S. Guillaumet,J. Kuss,Frederic Allibert,Gen Tsutsui,James Chingwei Li,Pierre Morin,Swati Mehta,R. Johnson,Lisa F. Edge,Shom Ponoth,T. Levin,S. Kanakasabapathy,Balasubramanian S. Pranatharthi Haran,Huiming Bu,J. L. Bataillon,Olivier Weber,O. Faynot,Emmanuel Josse,Michel Haond,Walter Kleemeier,Mukesh Khare,T. Skotnicki,Scott Luning,Bruce B. Doris,M. Celik,R. Sampson +38 more
TL;DR: Electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond, and BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.
Proceedings ArticleDOI
Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
Qing Liu,Atsushi Yagishita,Nicolas Loubet,Ali Khakifirooz,Pranita Kulkarni,T. Yamamoto,Kangguo Cheng,M. Fujiwara,Jin Cai,D. Dorman,Swati Mehta,Prasanna Khare,K. Yako,Yu Zhu,S. M. Mignot,S. Kanakasabapathy,Stephane Monfray,Frederic Boeuf,Charles W. Koburger,Hiroshi Sunamura,Shom Ponoth,Alexander Reznicek,Balasubramanian S. Pranatharthi Haran,A. Upham,R. Johnson,Lisa F. Edge,J. Kuss,T. Levin,N. Berliner,Effendi Leobandung,Thomas Skotnicki,Masami Hane,Huiming Bu,Kazunari Ishimaru,Walter Kleemeier,Mariko Takayanagi,Bruce B. Doris,R. Sampson +37 more
TL;DR: In this paper, a gate length of 25nm and competitive drive currents of 1.27 mV·µm were achieved by using a gate-first high-k/metal and raised source/drains (RSD).