F
Frederic Allibert
Researcher at Soitec
Publications - 126
Citations - 1389
Frederic Allibert is an academic researcher from Soitec. The author has contributed to research in topics: Silicon on insulator & Layer (electronics). The author has an hindex of 18, co-authored 114 publications receiving 1247 citations. Previous affiliations of Frederic Allibert include Commissariat à l'énergie atomique et aux énergies alternatives & Grenoble Institute of Technology.
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Journal ArticleDOI
Germanium-on-insulator (GeOI) substrates—A novel engineered substrate for future high performance devices
Takeshi Akatsu,Chrystel Deguet,L. Sanchez,Frederic Allibert,Denis Rouchon,Thomas Signamarcheix,C. Richtarch,Alice Boussagol,Virginie Loup,Frédéric Mazen,Jean-Michel Hartmann,Yves Campidelli,Laurent Clavelier,Fabrice Letertre,N. Kernevez,Carlos Mazure +15 more
TL;DR: In this article, the Smart Cut™ layer transfer technology is found to be the best method to form wafer-level GeOI structures of different diameters and thickness range down to
Proceedings ArticleDOI
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
Kangguo Cheng,Ali Khakifirooz,Nicolas Loubet,Scott Luning,Toshiharu Nagumo,Maud Vinet,Qing Liu,Alexander Reznicek,Thomas N. Adam,Sebastian Naczas,Pouya Hashemi,J. Kuss,James Chingwei Li,H. He,Lisa F. Edge,J. Gimbert,Prasanna Khare,Yu Zhu,Z. Zhu,Anita Madan,N. Klymko,S. Holmes,T. Levin,Alex Hubbard,R. Johnson,M. Terrizzi,Sean Teehan,A. Upham,G. Pfeiffer,T. Wu,A. Inada,Frederic Allibert,Bich-Yen Nguyen,L. Grenouillet,Y. Le Tiec,Romain Wacquez,Walter Kleemeier,R. Sampson,Robert H. Dennard,Tak H. Ning,Mukesh Khare,Ghavam G. Shahidi,Bruce B. Doris +42 more
TL;DR: A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths and modulates device Vt, thus providing an additional knob to enable multi-Vt while maintaining undoped channels for all devices.
Proceedings ArticleDOI
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
Qing Liu,M. Vinet,J. Gimbert,Nicolas Loubet,Romain Wacquez,L. Grenouillet,Y. Le Tiec,Ali Khakifirooz,Toshiharu Nagumo,Kangguo Cheng,H. Kothari,Chanemougame Daniel,F. Chafik,S. Guillaumet,J. Kuss,Frederic Allibert,Gen Tsutsui,James Chingwei Li,Pierre Morin,Swati Mehta,R. Johnson,Lisa F. Edge,Shom Ponoth,T. Levin,S. Kanakasabapathy,Balasubramanian S. Pranatharthi Haran,Huiming Bu,J. L. Bataillon,Olivier Weber,O. Faynot,Emmanuel Josse,Michel Haond,Walter Kleemeier,Mukesh Khare,T. Skotnicki,Scott Luning,Bruce B. Doris,M. Celik,R. Sampson +38 more
TL;DR: Electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond, and BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.
Journal ArticleDOI
Impact of free surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization
TL;DR: Hovel et al. as mentioned in this paper investigated the influence of top free-surface states on the pseudo-MOSFET characteristics by comparing passivated versus nonpassivated samples, and the parameters of concern, investigated here, are carrier mobility, density of interface states, threshold (VT), and flatband (VFB) voltages.
Journal ArticleDOI
The multiple-gate mos-jfet transistor
TL;DR: The MOS-JFET as discussed by the authors combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body.