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[서평]「Computer Organization and Design, The Hardware/Software Interface」

The fifth generation (5G) wireless network technology is to be standardized by 2020, where main goals are to improve capacity, reliability, and energy efficiency, while reducing latency and massively increasing connection density. An integral part of 5G is the capability to transmit touch perception type real-time communication empowered by applicable robotics and haptics equipment at the network edge. In this regard, we need drastic changes in network architecture including core and radio access network (RAN) for achieving end-to-end latency on the order of 1 ms. In this paper, we present a detailed survey on the emerging technologies to achieve low latency communications considering three different solution domains: 1) RAN; 2) core network; and 3) caching. We also present a general overview of major 5G cellular network elements such as software defined network, network function virtualization, caching, and mobile edge computing capable of meeting latency and other 5G requirements.

A Survey on Low Latency Towards 5G: RAN, Core Network and Caching Solutions

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A systematic way to design concurrent multiband integrated LNAs in general is developed. Applications of concurrent multiband LNAs in concurrent multiband receivers together with receiver architecture are discussed. Experimental results of a dual-band LNA implemented in a 0.35-/spl mu/m CMOS technology as a demonstration of the concept and theory is presented.

/pdf/concurrent-multiband-low-noise-amplifiers-theory-design-and-1iy48rdapl.pdf

Concurrent multiband low-noise amplifiers-theory, design, and applications

As of today, the fifth generation (5G) mobile communication system has been rolled out in many countries and the number of 5G subscribers already reaches a very large scale. It is time for academia and industry to shift their attention towards the next generation. At this crossroad, an overview of the current state of the art and a vision of future communications are definitely of interest. This article thus aims to provide a comprehensive survey to draw a picture of the sixth generation (6G) system in terms of drivers, use cases, usage scenarios, requirements, key performance indicators (KPIs), architecture, and enabling technologies. First, we attempt to answer the question of "Is there any need for 6G?" by shedding light on its key driving factors, in which we predict the explosive growth of mobile traffic until 2030, and envision potential use cases and usage scenarios. Second, the technical requirements of 6G are discussed and compared with those of 5G with respect to a set of KPIs in a quantitative manner. Third, the state-of-the-art 6G research efforts and activities from representative institutions and countries are summarized, and a tentative roadmap of definition, specification, standardization, and regulation is projected. Then, we identify a dozen of potential technologies and introduce their principles, advantages, challenges, and open research issues. Finally, the conclusions are drawn to paint a picture of "What 6G may look like?". This survey is intended to serve as an enlightening guideline to spur interests and further investigations for subsequent research and development of 6G communications systems.

The Road Towards 6G: A Comprehensive Survey

This paper presents an alternative interpretation to Groszkowski's effect, which states that the oscillation frequency of a harmonic oscillator is shifted due to the higher harmonic currents flowing into the LC tank. Groszkowki's analysis starts by taking a strictly memoryless amplifier, to which he derives and expression for balance of reactive powers. Then he interprets the frequency shift as a matter of balance of reactive energy in the tank. Here we show that although a conductive amplifier is memoryless, it can still show phase shift at the fundamental tone. This is due to mixing of the fundamental and harmonics in the nonlinear i-v response of the amplifier. Now the new interpretation comes from the oscillation condition: if the amplifier shows phase shift, the tank needs to compensate it, and this causes the shift in the oscillation frequency. The mechanism is explained, analysed symbolically, and verified numerically.

/pdf/a-new-interpretation-to-groszkowski-s-effect-3t1ob07jlj.pdf

A New Interpretation to Groszkowski's Effect

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

Radio receiver equalisation to provide calibration accuracy in an analog filter, comprising: estimating a cutoff frequency for the analog filter, causing a filter tuning word to be modified based on the estimated cutoff frequency for the analog filter, determining a residual cutoff frequency mismatch for the analog filter, causing an equaliser configuration to be selected for a digital filter based on the determined residual cutoff frequency mismatch

Radio receiver equalisation

This paper concerns with the nonlinearity analysis and compensation of active phase shifters based on vector modulator topologies which utilize Gilbert cell type multipliers. In this respect, both frequency dependence and expansion behavior of such topologies are analyzed. Based on translinear circuits theory, log/anti-log nonlinear equations are transformed to algebraic linear equations and/or multiplication equations, which facilitates solution for such nonlinear equations. To validate the analyses, a 5-bit active phase shifter was designed and simulated in 0.13um HBT technology node. 3D electromagnetic simulation results verify the consistency of the analysis and proposed compensation technique.

/pdf/analysis-of-hbt-vector-modulator-phase-shifters-based-on-etvn2gwpjl.pdf

Analysis of HBT Vector Modulator Phase Shifters Based on Gilbert Cell for sub-THz Regimes

A Ka-band dual input, three stack power amplifier (PA) is designed and fabricated using 22nm CMOS FDSOI. The PA output matching is implemented with a transformer-based combiner, which allows tuning the load with bias and input drive settings. The PA shows maximum output power, gain, one dB output power compression point (P 1dB ) and power added efficiency (PAE) of 19.5dBm, 11.5dB, 14.1dBm and 17%, respectively, measured at 29.5 GHz. Measured amplitude to phase modulation (AM-PM) stays at very low level, below 0.7° up to P 1dB and below 2.6° up to P 3dB . With a 100 MHz 64-QAM OFDM signal the PA achieves 8% error vector magnitude (EVM) and -28dBc adjacent channel leakage ratio (ACLR) at 6.3dBm and 7.6dBm output channel power, respectively.

Aarno Parssinen

Papers

A New Interpretation to Groszkowski's Effect

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

Radio receiver equalisation

Analysis of HBT Vector Modulator Phase Shifters Based on Gilbert Cell for sub-THz Regimes

Ka-Band Dual Input Stacked 22 nm CMOS FDSOI Power Amplifier with Transformer-Based Power Combiner