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[서평]「Computer Organization and Design, The Hardware/Software Interface」

The fifth generation (5G) wireless network technology is to be standardized by 2020, where main goals are to improve capacity, reliability, and energy efficiency, while reducing latency and massively increasing connection density. An integral part of 5G is the capability to transmit touch perception type real-time communication empowered by applicable robotics and haptics equipment at the network edge. In this regard, we need drastic changes in network architecture including core and radio access network (RAN) for achieving end-to-end latency on the order of 1 ms. In this paper, we present a detailed survey on the emerging technologies to achieve low latency communications considering three different solution domains: 1) RAN; 2) core network; and 3) caching. We also present a general overview of major 5G cellular network elements such as software defined network, network function virtualization, caching, and mobile edge computing capable of meeting latency and other 5G requirements.

A Survey on Low Latency Towards 5G: RAN, Core Network and Caching Solutions

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A systematic way to design concurrent multiband integrated LNAs in general is developed. Applications of concurrent multiband LNAs in concurrent multiband receivers together with receiver architecture are discussed. Experimental results of a dual-band LNA implemented in a 0.35-/spl mu/m CMOS technology as a demonstration of the concept and theory is presented.

/pdf/concurrent-multiband-low-noise-amplifiers-theory-design-and-1iy48rdapl.pdf

Concurrent multiband low-noise amplifiers-theory, design, and applications

As of today, the fifth generation (5G) mobile communication system has been rolled out in many countries and the number of 5G subscribers already reaches a very large scale. It is time for academia and industry to shift their attention towards the next generation. At this crossroad, an overview of the current state of the art and a vision of future communications are definitely of interest. This article thus aims to provide a comprehensive survey to draw a picture of the sixth generation (6G) system in terms of drivers, use cases, usage scenarios, requirements, key performance indicators (KPIs), architecture, and enabling technologies. First, we attempt to answer the question of "Is there any need for 6G?" by shedding light on its key driving factors, in which we predict the explosive growth of mobile traffic until 2030, and envision potential use cases and usage scenarios. Second, the technical requirements of 6G are discussed and compared with those of 5G with respect to a set of KPIs in a quantitative manner. Third, the state-of-the-art 6G research efforts and activities from representative institutions and countries are summarized, and a tentative roadmap of definition, specification, standardization, and regulation is projected. Then, we identify a dozen of potential technologies and introduce their principles, advantages, challenges, and open research issues. Finally, the conclusions are drawn to paint a picture of "What 6G may look like?". This survey is intended to serve as an enlightening guideline to spur interests and further investigations for subsequent research and development of 6G communications systems.

The Road Towards 6G: A Comprehensive Survey

In accordance with an example embodiment of the present invention, an apparatus for transmission is disclosed comprising a processor (420) configured to receive data and to form data packets, a radio frequency transmitter configured to transmit the data packets, a monitor (404) configured to evaluate resource utilization of the radio frequency transmitter and to provide a resource utilization rate, and a controller (404), wherein the controller (404) is configured to instruct the processor (420) to form multiple output or single output data packets to the radio frequency transmitter based on the resource utilization rate.

Method and apparatus for mimo transmission

This paper presents a broadband linearization technique that can be used for mmWave amplifier circuits. It is based on the well-known principle of derivative superposition, where FETs with different operating points are connected in parallel to generate mutually cancelling third order intermodulation distortion (IM3) products. It is demonstrated by measurements in excess of 10 dB improvement in IM3 obtained from 1 GHz to 30 GHz, practically free by connecting a NMOS with very low gate bias in parallel of an amplifying NMOS. The reasons and limits of the cancellation are discussed. The inherent broadbandness of the technique makes it extremely suitable to be used in CMOS mmWave circuits.

/pdf/broadband-linearization-technique-for-mmwave-circuits-20ihx07z3s.pdf

Broadband Linearization Technique for mmWave Circuits

This paper presents a fully integrated phased array receiver containing two four element radio frequency (RF) beamforming receivers supporting two multiple-input multiple-output channels. The receivers are designed and fabricated using 45 nm CMOS SOI technology. A 10 bit IQ vector modulator phase shifter (IQVM) is implemented in RF signal paths to control the phase and amplitude of the received signal before combining. Each IQVM provides 360° phase shift control and 17 dB gain variation. An off-chip, simultaneous high-Q impedance matching and bandpass filtering technique for each low-noise amplifiers is presented using non-uniform transmission line segments. Measured downconversion gain at 100 MHz intermediate frequency and noise figure (NF) of a single path are 23 and 5.4 dB, respectively, giving estimated 3.4 dB NF for a single element when simulated PCB and matching losses are taken into account. 1 dB compression point and Input third-order intercept point (IIP3) are − 37 and − 28 dBm, respectively. Each four-element receiver consumes 486 mW DC power from 1.2 V power supply. Total area of two receivers is 5.69 mm2.

/pdf/a-fully-integrated-4-2-element-cmos-rf-phased-array-receiver-18i73a33lg.pdf

A fully integrated 4 × 2 element CMOS RF phased array receiver for 5G

The present invention relates to a communication system comprising devices (2a-2d) having means for short range communication using a certain frequency band. The frequency band is divided into communication channels. In the communication system at least a first device class and a second device class are defined for categorizing the devices. The device class determines at least which communication channels the device can use in communication.

System, method and device for performing communication in a short range radio network

The use of subsampling for frequency downconversion and related tradeoffs in radio receivers are discussed. It is found that using the highest possible sampling frequency both relaxes anti-alias filtering requirements and reduces the effect of clock jitter. However, high-speed switched-capacitor circuits are difficult to design and they are typically power consuming. A switched-capacitor decimation sampler is proposed as a way to achieve more optimal sampling frequencies both at the input and the output of the sampler. The design and experimental results of a 3-V 230-MHz CMOS decimation subsampler are presented. The sampler achieves an input referred noise density of 44 nV//spl radic/Hz, an IIP/sub 3/ of +19.5 dBV, and a -52-dBc worst mixing product from clock skew with a 200-MHz input.

Aarno Parssinen

Papers

Method and apparatus for mimo transmission

Broadband Linearization Technique for mmWave Circuits

A fully integrated 4 × 2 element CMOS RF phased array receiver for 5G

System, method and device for performing communication in a short range radio network

A 3-V 230-MHz CMOS decimation subsampler.