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[서평]「Computer Organization and Design, The Hardware/Software Interface」

The fifth generation (5G) wireless network technology is to be standardized by 2020, where main goals are to improve capacity, reliability, and energy efficiency, while reducing latency and massively increasing connection density. An integral part of 5G is the capability to transmit touch perception type real-time communication empowered by applicable robotics and haptics equipment at the network edge. In this regard, we need drastic changes in network architecture including core and radio access network (RAN) for achieving end-to-end latency on the order of 1 ms. In this paper, we present a detailed survey on the emerging technologies to achieve low latency communications considering three different solution domains: 1) RAN; 2) core network; and 3) caching. We also present a general overview of major 5G cellular network elements such as software defined network, network function virtualization, caching, and mobile edge computing capable of meeting latency and other 5G requirements.

A Survey on Low Latency Towards 5G: RAN, Core Network and Caching Solutions

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A systematic way to design concurrent multiband integrated LNAs in general is developed. Applications of concurrent multiband LNAs in concurrent multiband receivers together with receiver architecture are discussed. Experimental results of a dual-band LNA implemented in a 0.35-/spl mu/m CMOS technology as a demonstration of the concept and theory is presented.

/pdf/concurrent-multiband-low-noise-amplifiers-theory-design-and-1iy48rdapl.pdf

Concurrent multiband low-noise amplifiers-theory, design, and applications

As of today, the fifth generation (5G) mobile communication system has been rolled out in many countries and the number of 5G subscribers already reaches a very large scale. It is time for academia and industry to shift their attention towards the next generation. At this crossroad, an overview of the current state of the art and a vision of future communications are definitely of interest. This article thus aims to provide a comprehensive survey to draw a picture of the sixth generation (6G) system in terms of drivers, use cases, usage scenarios, requirements, key performance indicators (KPIs), architecture, and enabling technologies. First, we attempt to answer the question of "Is there any need for 6G?" by shedding light on its key driving factors, in which we predict the explosive growth of mobile traffic until 2030, and envision potential use cases and usage scenarios. Second, the technical requirements of 6G are discussed and compared with those of 5G with respect to a set of KPIs in a quantitative manner. Third, the state-of-the-art 6G research efforts and activities from representative institutions and countries are summarized, and a tentative roadmap of definition, specification, standardization, and regulation is projected. Then, we identify a dozen of potential technologies and introduce their principles, advantages, challenges, and open research issues. Finally, the conclusions are drawn to paint a picture of "What 6G may look like?". This survey is intended to serve as an enlightening guideline to spur interests and further investigations for subsequent research and development of 6G communications systems.

The Road Towards 6G: A Comprehensive Survey

A time-domain duplexing radio frequency (RF) front-end with integrated antenna switch, power amplifier (PA), and low noise amplifier (LNA) was developed aiming for fifth-generation communication (5G) applications covering 24–28 GHz frequency range Antenna switch utilizes pre-existing LNA input matching network together embedded with grounded shunt transistor switch to provide sufficient isolation of receive side from PA Respectively, high impedance of off-state PA is assumed to achieve acceptable receive performance Resulting output power is 136 dBm with 15 dB of peak small-signal gain at 28 GHz Maximum average channel power was 48 dBm with 100 MHz 64-QAM OFDM signal within 5G adjacent channel power ratio and error vector magnitude specifications Receive (RX) front-end achieves 5 dB noise figure at 24 GHz and 7 dB of peak gain Performances of amplifiers degraded only by 2 dB from switch integration The front-end dissipates 183 and 46 mW of power in transmit and receive mode, respectively The simplistic design method minimizes cost both in circuit area (only 019 mm2) and design time making this front-end an attractive alternative in massive phased array applications using 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon on insulator process

/pdf/ka-band-time-domain-multiplexing-front-end-with-minimum-rzqvsirg3w.pdf

Ka-band time-domain multiplexing front-end with minimum switch area utilization on 22 nm fully depleted silicon-on-insulator CMOS technology

The invention relates to a control unit configured to search for at least one predetermined conversion function, check a system time of at least one radio protocol, define a common time, convert the system time of at least one radio protocol to the common time with the at least one conversion function and process control commands in the common time, and/or convert the common time to the system time of at least one radio protocol with the at least one conversion function and process control commands in the system time

Aarno Parssinen

Papers

Ka-band time-domain multiplexing front-end with minimum switch area utilization on 22 nm fully depleted silicon-on-insulator CMOS technology

Enhancing interoperatibility among radio protocols of a multimode device

Mimo or simo transmission based on resource utilization data