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[서평]「Computer Organization and Design, The Hardware/Software Interface」

The fifth generation (5G) wireless network technology is to be standardized by 2020, where main goals are to improve capacity, reliability, and energy efficiency, while reducing latency and massively increasing connection density. An integral part of 5G is the capability to transmit touch perception type real-time communication empowered by applicable robotics and haptics equipment at the network edge. In this regard, we need drastic changes in network architecture including core and radio access network (RAN) for achieving end-to-end latency on the order of 1 ms. In this paper, we present a detailed survey on the emerging technologies to achieve low latency communications considering three different solution domains: 1) RAN; 2) core network; and 3) caching. We also present a general overview of major 5G cellular network elements such as software defined network, network function virtualization, caching, and mobile edge computing capable of meeting latency and other 5G requirements.

A Survey on Low Latency Towards 5G: RAN, Core Network and Caching Solutions

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A systematic way to design concurrent multiband integrated LNAs in general is developed. Applications of concurrent multiband LNAs in concurrent multiband receivers together with receiver architecture are discussed. Experimental results of a dual-band LNA implemented in a 0.35-/spl mu/m CMOS technology as a demonstration of the concept and theory is presented.

/pdf/concurrent-multiband-low-noise-amplifiers-theory-design-and-1iy48rdapl.pdf

Concurrent multiband low-noise amplifiers-theory, design, and applications

As of today, the fifth generation (5G) mobile communication system has been rolled out in many countries and the number of 5G subscribers already reaches a very large scale. It is time for academia and industry to shift their attention towards the next generation. At this crossroad, an overview of the current state of the art and a vision of future communications are definitely of interest. This article thus aims to provide a comprehensive survey to draw a picture of the sixth generation (6G) system in terms of drivers, use cases, usage scenarios, requirements, key performance indicators (KPIs), architecture, and enabling technologies. First, we attempt to answer the question of "Is there any need for 6G?" by shedding light on its key driving factors, in which we predict the explosive growth of mobile traffic until 2030, and envision potential use cases and usage scenarios. Second, the technical requirements of 6G are discussed and compared with those of 5G with respect to a set of KPIs in a quantitative manner. Third, the state-of-the-art 6G research efforts and activities from representative institutions and countries are summarized, and a tentative roadmap of definition, specification, standardization, and regulation is projected. Then, we identify a dozen of potential technologies and introduce their principles, advantages, challenges, and open research issues. Finally, the conclusions are drawn to paint a picture of "What 6G may look like?". This survey is intended to serve as an enlightening guideline to spur interests and further investigations for subsequent research and development of 6G communications systems.

The Road Towards 6G: A Comprehensive Survey

How well do upper millimeter-wave and terahertz frequency bands enable wireless communications? In this work, we approximate the current and estimate the future communication potential with emphasis on antenna and radio frequency hardware technologies, and radio propagation challenges. This is done by performing link budget evaluations with justified estimates of link budget calculus terms, such as the achievable or required noise figure, transmit power, and antenna gain. Estimates are based on current enabling technologies and needs to advance those. From the RF viewpoint, the bottlenecks are in generating sufficiently high transmit power and low noise with the support of very high antenna gains. As an example, we discuss opportunities around 300 GHz frequency. Challenges to support 100 Gb/s bit rate at 30 GHz bandwidth on 10 m link distance is analyzed for different kinds of devices.

/pdf/thz-radio-communication-link-budget-analysis-toward-6g-47v3lczy5m.pdf

THz Radio Communication: Link Budget Analysis toward 6G

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-/spl mu/m SiGe BiCMOS process and is characterized at 900 MHz.

/pdf/calibration-techniques-of-active-bicmos-mixers-3tu1er809q.pdf

Calibration techniques of active BiCMOS mixers

Spectrum sensing is needed in cognitive radios to provide information about the surrounding radio spectrum. This enables cognitive radio system to communicate among existing radio systems without interfering them. This paper describes an FPGA implementation of a cyclostationary feature detector, which has an improved detection performance achieved by decimation of the cyclic spectrum. Decimation also provides a simple way to control detection time and, thus, allows trading the detection time to better probability of detection and vice versa. Measured detection performance is presented and detection of a 802.11g WLAN signal from air is demonstrated.

Implementation of Cyclostationary Feature Detector for Cognitive Radios

Subharmonic sampling is a discrete-time solution to the signal downconversion problem. It can be used either to replace a traditional continuous-time mixer in a superheterodyne receiver or can be combined with other discrete-time analog signal processing blocks in novel receiver architectures. We present a 2-GHz bandwidth integrated mixer based on subharmonic sampling operating at sampling frequencies from 40 MHz to 1.5 GHz. The conversion efficiency is optimized by appropriate choice of the clock duty cycle. The sampler uses a two-diode topology with a 3-V supply. The downconversion loss for the passive sampler is 1 dB and the total system gain 3 dB, The mixer achieves IIP3 of +16-dBm and -1-dB compression +7 dBm for a single-tone input. The circuit was implemented with a 0.6-/spl mu/m GaAs metal-semiconductor field effect transistor (MESFET) process.

A 2-GHz subharmonic sampler for signal downconversion

Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises a first sampler circuit (302, 510, 803, 910) coupled to the input, a second sampler circuit (303, 520, 804, 920) coupled to the input, a buffering component (309, 509, 809, 903, 904) coupled to the output and buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985). The buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.

Aarno Parssinen

Papers

THz Radio Communication: Link Budget Analysis toward 6G

Calibration techniques of active BiCMOS mixers

Implementation of Cyclostationary Feature Detector for Cognitive Radios

A 2-GHz subharmonic sampler for signal downconversion

Method and circuit for sampling a signal at high sampling frequency