Showing papers by "Chenming Hu published in 2005"

Semiconductor device and method of fabricating the same

Abstract: Semiconductor device and method of fabricating the same. A semiconductor device in accordance with the invention includes a gate dielectric overlying a channel region. A source region and a drain region are disposed on opposing sides of the channel region, where the channel region is comprised of a first semiconductor material and the source and drain regions are comprised of a second semiconductor material. A gate electrode overlies the gate dielectric and first and second spacers are formed on sides of the gate electrode, wherein each of the spacers includes a void adjacent to the channel region.

Semiconductor nano-wire devices and methods of fabrication

Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.

Electromigration and adhesion

Abstract: It has been demonstrated that, in those instances where electromigration-induced mass transport is dominated by interfacial diffusion, the adhesion at the interface where mass transport is primarily taking place is related to the electromigration flux. Furthermore, it is shown that the cohesive energy of the interface is directly related to the activation energy for diffusion.

Advanced Compact Models for MOSFETs

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Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof

Abstract: A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one of p-type and n-type and the first doped electrode comprises the other of p-type and n-type. The device further comprises a second transistor having a charge carrier type opposite the first charge carrier type. The second transistor comprises the high-k gate dielectric, and a second doped electrode, wherein the second doped electrode comprises the other of p-type and n-type.

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Abstract: On-chip global interconnect exhibits clear frequency dependence in both resistance (R) and inductance ( L). In this paper, its impact on modern digital and radio frequency (RF) circuit design is examined. First, a physical and compact ladder circuit model is developed to capture this behavior, which only employs frequency independent R and L elements, and thus, supports transient analysis. Using this new model we demonstrate that the use of dc values for R and L is sufficient for timing analysis (i.e., 50% delay and slew rate) in digital designs. However, RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.

High performance semiconductor devices fabricated with strain-induced processes and methods for making same

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Charge-based core and the model architecture of BSIM5

Abstract: The paper outlines the charge-based core and the architecture of the BSIM5 MOSFET model for sub-100 nm CMOS circuit simulation. The BSIM5 model is a continuous, completely symmetric and accurate non charge-sheet based MOS transistor model derived from the basic device physics, including various physics effects. Comparison of the inversion charge between the BSIM5 prediction and self-consistent numerical solution shows good agreement. The demonstration of fully symmetric characteristics of BSIM5, such as channel current and its high-order derivative in the Gummel symmetry test, and charge and trans-capacitances in a SPICE simulation, also implies BSIM5 is the physically symmetric MOSFET model valid for RF-analog circuit simulations.

Relaxed silicon germanium substrate with low defect density

Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Tamper-Proof Content-Playback System Offering Excellent Copyright Protection

Abstract: To protect copyright, the present invention provides a tamper-proof content-playback system Its content-playback unit has the following I/O characteristics: A) at least a portion of its content input(s) is encrypted digital signals; B) at least a portion of its content output(s) is non-digital (eg analog) or non-electrical (eg image) signals Only secure data connections are allowed for decrypted contents inside the content-playback unit Accordingly, its components are preferably integrated into: a single chip, a single package, or a chip/package-on-panel

Method of fabricating a non-floating body device with enhanced performance

Abstract: Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.

Compact modeling of FinFETs featuring independent-gate operation mode

Abstract: This paper describes the concept of the dynamic V/sub TH/ control in the compact modeling of FinFET. The model is implemented into Berkeley SPICE3 and verified with multiple-dimensional device simulator.

Hybrid fractional-bit systems

Abstract: The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized. Hybrid N-ary system can be used to improve manufacturing yield and endurance lifetime.

Next generation CMOS compact models for RF and microwave applications

Abstract: Commercial CMOS chips routinely operate at frequencies up to 5 GHz and exciting new opportunities exists in higher frequency bands such as 3-10 GHz, 17 GHz, 24 GHz, and 60 GHz. The Berkeley Wireless Research Center has demonstrated that standard 130 nm CMOS technology is capable of operation up to 60 GHz, enabling a host of new mm-wave applications such as Gb/s WLAN and compact radar imaging. Will circuit design and compact modeling continue along the same course, or is a new microwave design methodology required? This paper highlights the design and modeling challenges in moving up to these higher frequencies. A merger of RF and microwave design perspectives is used to offer insight into the problem. The paper discusses requirements for a next generation compact model to meet these challenges and offers potential solutions.

Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer

Abstract: A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantially flat top electrode overlies said capacitor dielectric. The top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Partial replacement silicide gate

Abstract: A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer. A top layer is formed over the dielectric layer. The gate dielectric, the silicon-containing layer, the dielectric layer, and the top layer are patterned into a gate stack. A spacer is formed along an edge of the gate stack. The top layer and the dielectric layer are removed. A metal layer is deposited on the silicon-containing layer and silicided.

Semiconductor device and fabrication method thereof

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first epitaxial layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric

Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Semiconductor structure having selective silicide-induced stress and a method of producing same

Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

A compact model to predict quantized sub-band energy levels and inversion layer centroids of MOSFETs with a parabolic potential well approximation

Abstract: A compact model to predict sub-band energy levels and inversion charge centroids in the MOSFET surface inversion layer has been presented in this paper for parabolic potential well approximation. Based on a coupled solution of the Schrodinger equation and the Poisson equation following the WKB method, one transcendental equation of the sub-band energy level has been rigorously derived and then the approximate analytical solutions for the sub-band energy levels and the inversion charge centroids have been obtained. The analytical results are compared with the numerical data and a good agreement between the analytical and numerical is found.

MOS device and fabrication method thereof

Abstract: A MOS device and fabrication method of the same. The MOS device of the invention includes a substrate. A gate electrode is disposed over the substrate. A pair of source/drain regions are respectively disposed in the substrate on both sides of the gate electrode. A stress-buffering lining is conformably disposed on both sides of the gate electrode and partially extends to the surface of the substrate and a stress layer is disposed over the gate electrode, the stress-buffering lining and the source/drain regions and contacts the stress-buffering lining to enhance stresses in a channel region in the substrate below the gate electrode.

An interconnect structure and method for fabricating the same

Abstract: Composite ALD-formed diffusion barrier layers In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD