Showing papers by "Eric Beyne published in 2013"

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

Abstract: Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

Abstract: This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

Interposer technology for high band width interconnect applications

Abstract: Silicon Interposer provides very high density interconnect combining through Silicon vias and fine wiring. The concept reported in this paper is implementing integrated power supply layers with decoupling metal insulator metal decoupling capacitor to enhance signal integrity. In addition an upscale damascene process was used to fabricate high density and high bandwidth routing interconnect. A detailed characterization of the warpage behavior along the processing steps and electrical characterization of interposer TSV and BEOL are reported.

Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications

Abstract: Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding has become a key element in device processing over the past years. Today, although solutions for wafer support systems have made great progress in terms of process performance, thin wafer debonding and handling remains extremely challenging. Our motivation to move away from thermoplastic high temperature melt debonding materials to room temperature debondable materials is clearly exposed in this paper: we describe the process integration and manufacturing aspects of the Brewer Science® ZoneBOND® temporary bonding process, as a one-to-one alternative to the Brewer Science® WaferBOND® HT-10.10 slide debonding material. Process issues related to the material integration into complex 3D flows as well as key learnings are described in details. One important modification that was required is related to the edge-trimming process that is typically performed on the active device wafer prior to bonding and grinding. The ZoneBOND® material was found not to be compatible with this process, resulting in permanent defects and damages during grinding. To resolve this issue, the process flow was modified to an edge-trimming after wafer bonding approach. Finally, the room temperature debonding process is fully described.

Key elements for sub-50μm pitch micro bump processes

Abstract: The ever need for more dense 3D integration or increasing number of IOs requires a scaling down of micro bump dimension and pitch. Scaling although adds high requirements on micro bump process technology and stacking accuracy. It is shown that by working on the micro bump sizes, increased stacking accuracy can be achieved. Integration scheme and process parameters need to be carefully tuned to allow a stable Cu(Ni)Sn micro bumping process. Analysis of the micro bumps is done by shear tests.

High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias

Abstract: Among the technological developments pushed by the emergence of 3D-ICs, Through Silicon Via (TSV) technology has become a standard element in device processing over the past years. As volume increases, defect detection in the overall TSV formation sequence is becoming a major element of focus nowadays. Robust methods for in-line void detection during TSV processing are therefore needed especially for scaled down dimensions. Within this framework, the current contribution describes the successful application of innovative GHz Scanning Acoustic Microscopy (SAM) to TSV void detection in a via-middle approach.

Impact of barrier integrity on liner reliability in 3D through silicon vias

Abstract: For 3D chip stacking using Cu through silicon vias (TSV's), dielectric liner reliability is crucial and is closely related to the barrier integrity. In this study, two different Cu barriers are compared in terms of dielectric liner reliability. By using two stress modes, where different voltage polarities are applied to the TSV, the impact of barrier integrity on liner reliability is segregated and PVD Ti is shown to be superior to PVD Ta for our particular liner. The field acceleration factors are extracted using classical TDDB and from controlled ramp rates, where a good match is found between the two methods. When applying a positive voltage to the TSV during stress, a bimodal distribution of the TDDB lifetime is observed for the PVD Ta barrier. This is linked to a competition between Cu induced dielectric breakdown and intrinsic dielectric breakdown.

Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance

Abstract: In the study, we report for the first time a novel concept for the mitigation of the TSV-induced stress on the CMOS device performance. This solution consists in selectively integrating an airgap at the time of via-middle TSV processing. In addition to the expected benefits in term of stress management, this new approach is also cost effective, as the TSV processing steps, such as deep silicon etching, Cu electroplating, and chemical mechanical polishing remain unchanged. The processing development and the results of the morphological and electrical characterization are given in details in this study. All in all, TSV with integrated airgap is a very versatile building block for TSV integration in presence of stress sensitive next generation of CMOS devices.

Design issues in heterogeneous 3D/2.5D integration

Abstract: Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, the design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimisation techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and the practical EDA tool chain that covers different aspects of the design flow and is specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generations and Design-for-Test (DfT). The application of the tool chain is illustrated using concrete example of a real-world design, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies.

Si interposer build-up options and impact on 3D system cost

Abstract: The requirements for embedded system functionalities promote stacked integration solutions where interposers are used as large carriers to provide dense interconnections among functional dies. Using the cost model developed at imec, the processing cost of different interposer features is analyzed. Build-up options of various interposer configurations are compared and the additional cost of the interposer component is highlighted. In addition the impact of interposer testing on the system cost is investigated for different interposer substrate areas.

Effect of TSV presence on FEOL yield and reliability

Abstract: In this work we evaluate the impact of TSV processing and proximity on transistor performance and reliability by monitoring key device parameters after thermal cycling and thermal storage. No transistor degradation related to potential barrier failure, liner breakdown or Cu diffusion was observed and it is concluded that when respecting the keep out zone, the FEOL yield and reliability is not affected by TSV processing.

Numerical comparison of the thermal performance of 3D stacking and Si interposer based packaging concepts

Abstract: In this paper, the thermal performance and the thermal die-to-die coupling are compared for the case of a 3D stacked configuration and a Si TSV-interposer by means of detailed thermal finite element simulations. The comparison is applied to packages with two components: 10×10mm2 logic chip and a 2×10mm2 temperature sensitive SerDes chip. A one-to-one comparison is made for package configurations without heat sink and for packages with integrated heat spreader and high performance heat sink.

RF characterization and modeling of through-silicon vias

Abstract: This paper investigates the RF properties of 5 μm diameter/50 μm depth through-silicon vias (TSVs) built in CMOS 65nm technology. An equivalent lump model of the TSVs was developed based on 3D full-wave electromagnetic simulations and was validated by RF measurements. Based on the validated TSV model, the crosstalk among the TSVs was addressed as a function of distance and frequency. An equivalent lump model of the TSV-to-TSV crosstalk was also developed. Good agreement was obtained between simulations and measurements. Additionally, the noise peak vs. TSV-to-TSV distance and the crosstalk noise as a function of rise time was also investigated. It was found that the crosstalk noise decreased and the noise width increased with increasing signal rise time. A short signal rise time should thus be applied only if high speed is really required.

Simulation of Cu pumping during TSV fabrication

Abstract: Using Finite element methods, a model to predict the Cu pumping in Through Silicon Vias (TSV) is built. The processes which a TSV undergoes after Cu electroplating are considered and the model is built in such a way that after each process sequence, the stress and strain data are transferred into the following sequence and used as input conditions. The stress and Cu pumping at the end of the simulations are extracted and compared with experimental results. This allows virtual studies and predictions of Cu pumping for different TSV geometries and the possible effects of Back-end of line (BEOL) layers.

Convolution based compact thermal model for 3D-ICs: Methodology and accuracy analysis

Abstract: Thermal analysis is essential in 3D-IC technology due to the reduced footprint and higher power densities compared to conventional 2D packaging [1]. Compact thermal models (CTM) are being developed for fast evaluation of the thermal distribution in the 3D packages. The CTM discussed in this paper is based on the Green's function theory and exploits convolution and fast Fourier transform to compute the temperature profiles starting from matrices storing the power dissipation densities (power maps) and the temperature responses to hot spots. Detailed accuracy assessments are presented for the grid size and for the number of images to be considered for an accurate modelling of the lateral insulating boundary conditions. A two dies stack case study is also analysed showing good agreement with the finite element model results (error less than 0.5%). Finally, the algorithm computational time is discussed indicating a O(N logN) behaviour where N is the number of elements in the matrices.

Wafer reconstruction: An alternative 3D integration process flow

Abstract: Wafer reconstruction is a process of forming an integral handle-able wafer by filling the gaps between the dies after die-to-wafer assembly to allow for further processing on the landing wafer, e.g. thinning, redistribution layer deposition, and bumping. This paper examines key aspects and challenges of different wafer reconstruction process flows. Based on analytical and finite element method modeling, guidelines for material selection and structural design are generated. One selected process flow is successfully demonstrated in a typical 300 mm eWLB production environment, proving the feasibility of wafer reconstruction as a 3D integration process flow.

Metrology and inspection challenges for manufacturing 3D stacked IC's

Abstract: In this paper we discuss the numerous metrology and inspection challenges that need to be overcome to really have high volume manufacturing of 3D integrated chips. The key metrology and inspections issues are addressed module wise. We start with the TSV module then move on to the wafer bonding and thinning module. This is followed by the bumping module, de-bonding module and finally we finish with the stacking module. Within each of the modules we show the possible solutions for metrology and inspection and also discuss limitations of the available metrology and inspection if it is warranted.

Thermo mechanical challenges for processing and packaging stacked ultrathin wafers

Abstract: During the manufacturing of 3D stacked-die packaging structures, different operations such as micro bumps formation, underfilling, flip chip and overmold curing will introduce residual stresses, which will interact with subsequent service loads applied to the package and may also influence the growth of cracks in critical locations. In this work, the packaging of a 3D-RAM mounted on a logic die is simulated taking the thermal history into account by simulating the main process steps and by adapting the mechanical stiffness of the materials. The resulting stress/strain tensors are taken as initial condition of the following step and the mechanical properties of the new materials added to the process are adapted. The resulting stresses and strains at every step are extracted from the model to identify the most critical processing steps. A die to wafer approach is used for the stacking process as it allows the integration of heterogeneous and different die size. In this work we show the simulation results after each processing step for two die stacking approaches: (a) mold wafer reconstruction, (b) window wafer reconstruction. In the first case, high warpage is observed. In the second case, warpage is reduced but high stress concentration is observed in the logic die.

Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking

Abstract: The demands and challenges in pushing the limits of Moore's Law made the 3D IC stacking radiate the pressure for MPTs (materials, processes and tools) in keeping up with the technology. The 3D IC architecture design built around the TSVs, micro-bumps and thinned wafers/dies is the center of the show, of which the MPTs must conform and be viable to be part of the supporting cast. Underfilling's main objectives is to provide the mechanical stability for micro-bumps and prevents moisture between the resulting gap between dies before the 3D stack is sent for packaging. With several complexities in 3D stacking had to be considered and addressed in applying the underfill materials. Complexities such as the stacking options Die-to-Die (D2D) or Die-to-Wafer (D2W), the thicknesses of the dies to be stacked (~50 um die thickness), the thermo-compression bonding parameters to be used and the behavior of the underfill materials to the different process parameters had to considered during the characterization process of underfills.

Study of 3D process impact on advanced CMOS devices

Abstract: Through 3D-IC Integration is possible to put more transistors on the same footprint without the need to shrink transistor sizes. As for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing. In this work we introduce the several processes to generate 3D stacked devices. We focus on processes like TSV, wafer thinning, backside passivation, back side RDL (Re-Distribution Layer), front side and backside μbumping. We report on the characterization of the effects on transistor devices due to TSV proximity, wafer thinning and die stacking. The transistor devices are based on imec CMOS technology and are manufactured on 300mm diameter wafers. The wafers are fully processed with Front End of Line (FEOL), Back End Of Line (BEOL), wafer thinning on Si carrier, back-side wafer bumping, carrier de-bonding, dicing and final 3D-stacking. We report the main electrical characterizations done to identify the impact of typical 3D processes on CMOS devices. The characterizations are performed in-line (clean room compatible test equipment) and confirmed offline (standard testing equipment out of clean room environment). To characterize the process steps of interest, we use dedicated test structures that are measured before and after the process. The dedicated test structures are mainly measured after wafer front side processing (FEOL and BEOL) and tested again after wafer thinning and after die stacking. The measured variations (typically ION currents) are later elaborated to illustrate the process effect. In case of 3D stacks, the characterization is executed for two-dies stacking. To have an assessment of the 3D stacking yield, the dies are connected by TSVs-μbumps in several daisy chain configurations.

Method for producing contact areas on a semiconductor substrate

Abstract: The present invention is related to a method for producing hollow contact areas suitable for insertion bonding, formed on a semiconductor substrate (1) comprising a stack of one or more metallization layers on its surface. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist material and the plasma etch parameters are chosen so as to obtain openings with sloped sidewalls that have a predefined slope, due to the controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during the etch step. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric is planarized using Chemical Mechanical Polishing, leading to mutually isolated contact areas. An array of such areas can be produced having smaller pitch compared to prior art arrays. The invention is equally related to components obtainable by the method of the invention, and to a package comprising such components.

Mimcap structure in a semiconductor device package

Abstract: The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.

IC-Package Interaction

Abstract: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing k value. These so-called (ultra) low-k materials have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC's use thinned dies (down to 25μm) which can cause much higher stresses at transistor level, resulting in mobility shifts.