http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

/pdf/a-10-bit-100-ms-s-reference-free-sar-adc-in-90-nm-cmos-4b9jo24381.pdf

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

/pdf/behavioral-modeling-of-switched-capacitor-sigma-delta-33360hldmd.pdf

Behavioral modeling of switched-capacitor sigma-delta modulators

We present a bandgap circuit capable of generating a reference voltage of 0.53 V. The circuit, implemented In a submicron BiCMOS technology, operates with a supply voltage of 1 V, consuming 92 /spl mu/W at room temperature. In the bandgap circuit proposed, we use a nonconventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1-V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 7.5 ppm/K of temperature coefficient and 212 ppm/V of supply voltage dependence, without requiring additional operational amplifiers or complex circuits for the curvature compensation.

/pdf/curvature-compensated-bicmos-bandgap-with-1-v-supply-voltage-2g1t6by4d8.pdf

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

This book is the first graduate-level textbook presenting a comprehensive treatment of Data Converters. It provides comprehensive definition of the parameters used to specify data converters, and covers all the architectures used in Nyquist-rate data converters. The book uses Simulink and Matlab extensively in examples and problem sets. This is a textbook that is also essential for engineering professionals as it was written in response to a shortage of organically organized material on the topic. The book assumes a solid background in analog and digital circuits as well as a working knowledge of simulation tools for circuit and behavioral analysis.

Data converters

The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

/pdf/a-9-4-enob-1v-3-8mw-100ks-s-sar-adc-with-time-domain-3dv3etfcj7.pdf

Franco Maloberti

Papers

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Behavioral modeling of switched-capacitor sigma-delta modulators

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

Data converters

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator