Showing papers by "John H. Magerlein published in 2007"

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

Abstract: This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

Interconnects in the third dimension: design challenges for 3D ICs

Abstract: Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two- dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.

High performance and subambient silicon microchannel cooling

Abstract: High performance single-phase Si microchannel coolers have been designed and characterized in single chip modules in a laboratory environment using either water at 22°C or a fluorinated fluid at temperatures between 20 and -40° C as the coolant. Compared to our previous work, key performance improvements were achieved through reduced channel pitch (from 75 to 60 microns), thinned channel bases (from 425 to 200 microns of Si), improved thermal interface materials, and a thinned thermal test chip (from 725 to 400 microns of Si). With multiple heat exchanger zones and 60 micron pitch microchannels with a water flow rate of 1.25 1pm, an average unit thermal resistance of 15.9 C mm 2 /W between the chip surface and the inlet cooling water was demonstrated for a Si microchannel cooler attached to a chip with Ag epoxy. Replacing the Ag epoxy layer with an In solder layer reduced the unit thermal resistance to 12.0 C mm 2 /W. Using a fluorinated fluid with an inlet temperature of -30°C and 60 micron pitch microchannels with an Ag epoxy thermal interface layer, the average unit thermal resistance was 25.6 C mm 2 /W. This fell to 22.6 C mm 2 /W with an In thermal interface layer. Cooling >500 W/cm 2 was demonstrated with water. Using a fluorinated fluid with an inlet temperature of -30° C, a chip with a power density of 270 W/cm 2 was cooled to an average chip surface temperature of 35°C. Results using both water and a fluorinated fluid are presented for a range of Si microchannel designs with a channel pitch from 60 to 100 microns.

High-efficiency 60 GHZ antenna fabricated using low-cost silicon micromachining techniques

Abstract: In this paper, a miniature, multi-functional Si-based packaging technology which can reduce the size and cost and increase the performance of a wide range of millimeter wave systems is proposed. High density capacitors, low temperature coefficient resistors, high-Q inductors, low-loss transmission lines, filters and antennas can all be built within the Si package using standard semiconductor fabrication methods with very high manufacturing precision compared to conventional packaging technologies. Fine pitch metal bumps can be used to attach RF IC's and other components, while bonding can provide hermetic sealing where required. Vias through the Si package eliminates inductive bond wires and minimize parasitics at millimeter wave frequencies. By integrating both antenna and an RF IC in one single package, all high frequency signals are confined within the package and only baseband signals connected to the external package.

High-efficiency 60 ghz antenna fabricated using low-cost silicon

Abstract: In this paper, a miniature, multi-functional Si-based packaging technology which can reduce the size and cost and increase the performance of a wide range of millimeter wave systems is proposed. High density capacitors, low temperature coefficient resistors, high-Q inductors, low-loss transmission lines, filters and antennas can all be built within the Si package using standard semiconductor fabrication methods with very high manufacturing precision compared to conventional packaging technologies. Fine pitch metal bumps can be used to attach RF IC's and other components, while bonding can provide hermetic sealing where required. Vias through the Si package eliminates inductive bond wires and minimize parasitics at millimeter wave frequencies. By integrating both antenna and an RF IC in one single package, all high frequency signals are confined within the package and only baseband signals connected to the external package.

Silicon based package

Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.